register-transfer level design

The absence of a systematic survey on large language models (LLMs) for Verilog RTL code generation hinders progress in hardware-AI co-design. Method: This paper conducts a cross-domain (software engineering/AI/EDA) analysis of 102 publications—70 peer-reviewed papers and 32 high-quality preprints—using bibliometric analysis, topic modeling, and cross-domain comparison, complemented by evaluation techniques including fine-tuning, prompt engineering, and functional correctness assessment. Contribution/Results: We introduce the first LLM-Verilog research map and a four-dimensional analytical framework addressing key research questions. Core bottlenecks are identified: architectural limitations of LLMs, scarcity of high-quality Verilog training data, and insufficient functional correctness guarantees. Furthermore, we propose a novel three-stage roadmap—“verifiable generation → hardware-aware alignment → EDA toolchain integration”—to guide future development, offering both theoretical foundations and practical pathways for LLM-driven RTL synthesis.

This work addresses the limited generalization capability of large language models (LLMs) across hardware description languages, particularly due to the absence of a systematic evaluation framework for VHDL. We propose the first unified framework for LLM-based VHDL generation and evaluation, introducing an automated, verifiable Verilog-to-VHDL benchmark conversion pipeline. The resulting VHDLBench dataset comprises over 200 VHDL modules, each accompanied by complete testbenches. Integrating automated data synthesis, the VUnit/GHDL verification toolchain, and multi-model comparative analysis, our framework enables the first comprehensive assessment of LLM-generated VHDL code in terms of compilability, executability, and functional correctness. This study reveals critical challenges posed by VHDL-specific semantics and structural constructs, laying the groundwork for multilingual hardware design automation.

Large language models (LLMs) face two key challenges in automated IC design: high failure rates in single-shot generation of complex RTL circuits, and poor alignment of conventional chain-of-thought (CoT) reasoning with expert design knowledge and formal verification requirements. Method: We propose VeriBToT, a novel LLM inference paradigm built upon the Backtrack-ToT framework. It integrates three core mechanisms: (1) self-decoupling—decomposing tasks hierarchically by design abstraction; (2) self-verification—embedding formal verification feedback into the reasoning loop; and (3) verifiability-driven tree-of-thought structure—enabling controllable reasoning direction and adjustable step granularity. VeriBToT deeply embeds the Design-for-Verification (DFV) principle into LLM inference, supporting backtracking-based optimization and modular code generation. Contribution/Results: Experiments demonstrate that VeriBToT significantly improves functional correctness and engineering usability of complex Verilog modules, while reducing human intervention frequency and token consumption.

To address the bottleneck in VLSI design where RTL-stage PPA (power, performance, area) estimation relies on time-consuming full synthesis—hindering rapid iteration—this paper proposes the first pre-synthesis machine learning framework operating directly on HDL source code. Our method introduces a bit-level Simple Operation Graph (SOG) representation that explicitly models the semantic mapping between RTL constructs and post-synthesis structures. We further design a standard-cell-library-aware tree-based architecture enabling end-to-end PPA prediction solely from Verilog code and library files, without requiring toggle information or synthesis intermediates. Evaluated on 147 industrial-scale RTL designs, our framework achieves 98% accuracy for worst negative slack (WNS), 98% for total negative slack (TNS), and 90% for power estimation—significantly outperforming prior approaches. The method demonstrates strong generalization across diverse designs and high engineering practicality.

Current large language models (LLMs) exhibit limited capability in RTL hardware design and verification—including code generation, formal/functional verification, debugging, specification alignment, and technical Q&A—and lack a systematic, real-world engineering benchmark. Method: We introduce CVDP, the first comprehensive RTL-oriented benchmark, comprising 783 expert-authored tasks spanning 13 industrial scenarios. It features a novel dual-mode task design—non-agent (direct code generation) and agent (interactive, stepwise reasoning)—to emphasize RTL reuse and collaborative verification challenges. We build an automated evaluation pipeline grounded in open-source EDA tools (Yosys/Icarus), integrating BLEU, LLM-based judging, and pass@1 metrics. Results: Experiments show state-of-the-art models achieve at most 34% pass@1 on code generation; performance degrades further on agent-mode tasks, exposing fundamental limitations of LLMs in hardware automation.

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This work addresses the challenges of directly generating RTL code with large language models (LLMs), which often suffer from verification difficulties, limited optimizability, and poor integration with compiler-driven design flows. To overcome these issues, the authors propose the CPPL framework, which introduces a compiler-mediated interface for the first time. By leveraging a Python-based frontend DSL and a JSON-encoded CPPL intermediate representation (IR), the approach reframes LLM-assisted hardware generation as a statically checkable frontend problem. The framework exploits the CIRCT infrastructure to automatically infer bit widths, validate structural correctness, and lower designs to synthesizable Verilog. This ensures generated circuits are type-safe, hierarchically structured, verifiable, and amenable to optimization. Evaluated on the RTLLM benchmark, the method significantly improves functional correctness and, after CIRCT-based optimization, yields synthesized circuits with substantially fewer AIG nodes.

This work addresses the challenges large language models face in generating synthesizable Verilog for hierarchical hardware designs, where inconsistent interfaces and fragmented structural context often lead to hallucinated wiring and loss of contextual coherence. To overcome these issues, the authors propose VeriGraphi, a novel framework that introduces, for the first time, a specification-anchored Hierarchical Design Anchor (HDA) knowledge graph as a structured intermediate representation. This graph explicitly models module hierarchy, port interfaces, wiring semantics, and dependency relationships. Leveraging a multi-agent collaborative approach, VeriGraphi enables progressive generation of pseudocode and Verilog code. Evaluated on NIST specifications and an RV32I processor case study, the method significantly improves functional correctness, reduces manual intervention, and achieves high-fidelity automated generation of hierarchical RTL.

This work proposes a novel approach to hardware security verification by automatically constructing end-to-end information flow paths from register transfer level (RTL) trace data. Unlike conventional information flow analyses that merely detect whether data flows between registers, the proposed method reconstructs complete propagation pathways of sensitive information at the RTL trace level for the first time. By integrating information flow tracking with specification mining techniques, the framework automatically generates and verifies security properties. This paradigm overcomes the limitations of pairwise flow detection, substantially enhancing the automation, precision in violation detection, and efficiency of system-wide security evaluation in hardware designs.