VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs

2026-04-15

AI Summary

This work addresses the challenges large language models face in generating synthesizable Verilog for hierarchical hardware designs, where inconsistent interfaces and fragmented structural context often lead to hallucinated wiring and loss of contextual coherence. To overcome these issues, the authors propose VeriGraphi, a novel framework that introduces, for the first time, a specification-anchored Hierarchical Design Anchor (HDA) knowledge graph as a structured intermediate representation. This graph explicitly models module hierarchy, port interfaces, wiring semantics, and dependency relationships. Leveraging a multi-agent collaborative approach, VeriGraphi enables progressive generation of pseudocode and Verilog code. Evaluated on NIST specifications and an RV32I processor case study, the method significantly improves functional correctness, reduces manual intervention, and achieves high-fidelity automated generation of hierarchical RTL.

Technology Category

• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Search and Retrieval-Augmented AI: Vertical and domain-specific search

Abstract

Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structured reasoning that human experts employ when translating complex specifications into RTL. When tasked with producing hierarchical Verilog, LLMs frequently lose context across modules, hallucinate interfaces, fabricate inter-module wiring, and fail to maintain structural coherence - failures that intensify as design complexity grows and specifications involve informal prose, figures, and tables that resist direct operationalization. To address these challenges, we present VeriGraphi, a framework that introduces a spec-anchored Knowledge Graph as the architectural substrate driving the RTL generation pipeline. VeriGraphi constructs a HDA, a structured knowledge graph that explicitly encodes module hierarchy, port-level interfaces, wiring semantics, and inter-module dependencies as first-class graph entities and relations. Built through iterative multi-agent analysis of the specification, this Knowledge Graph provides a deterministic, machine-checkable structural scaffold before code generation. Guided by the KG, a progressive coding module incrementally generates pseudo-code and synthesizable RTL while enforcing interface consistency and dependency correctness at each submodule stage. We evaluate VeriGraphi on a benchmark of three representative specification documents from the National Institute of Standards and Technology and their corresponding implementations, and we present a RV32I processor as a detailed case study to illustrate the full pipeline. The results demonstrate that VeriGraphi enables reliable hierarchical RTL generation with minimal human intervention for RISC-V, marking a significant milestone for LLM-generated hardware design while maintaining strong functional correctness.

Problem

• hierarchical RTL generation
• large language models
• hardware design
• Verilog synthesis
• specification-to-RTL translation

Innovation

• Knowledge Graph
• Hierarchical RTL Generation
• Multi-Agent Framework
• Verilog Synthesis
• Hardware Design Automation