VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

2024-08-15

arXiv.org

AI Summary

To address error-prone and inefficient manual Verilog coding in IC design, this paper proposes a multi-AI-agent collaborative framework for end-to-end Verilog generation and repair. Methodologically: (1) a graph-planning mechanism leveraging a task-circuit relational graph enhances mapping fidelity from natural-language specifications to RTL; (2) an AST-driven waveform tracing tool—integrated with symbolic execution—enables precise localization and automatic correction of functional bugs; (3) a closed-loop development pipeline unifies syntactic validation, hardware simulation, and dynamic waveform analysis. Evaluated on the VerilogEval-Human v2 benchmark, the framework achieves 94.2% syntactic and functional correctness—surpassing state-of-the-art methods by 33.9 percentage points—demonstrating substantial progress toward semantically correct, formally verifiable hardware design automation.

Technology Category

• Humans and AI: Human-Aware Planning and Behavior Prediction
• Planning, Routing, and Scheduling: Replanning and Plan Repair
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Search and Retrieval-Augmented AI: Agentic search
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using collaborative Verilog tools (i.e., syntax checker, simulator, and waveform tracer). Firstly, we propose a task planner that utilizes a novel Task and Circuit Relation Graph retrieval method to construct a holistic plan based on module descriptions. To debug and fix functional errors, we develop a novel and efficient abstract syntax tree (AST)-based waveform tracing tool, which is integrated within the autonomous Verilog completion flow. The proposed methodology successfully generates 94.2% syntactically and functionally correct Verilog code, surpassing the state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.

Problem

• Automates Verilog code generation to reduce human error in IC design.
• Develops AI agents for autonomous Verilog coding and error correction.
• Introduces AST-based waveform tracing for efficient debugging and functional fixes.

Innovation

• Autonomous AI agents for Verilog code generation
• Graph-based task planning for module descriptions
• AST-based waveform tracing for error debugging