Machine Learning Framework for Early Power, Performance, and Area Estimation of RTL

2025-02-22

AI Summary

To address the bottleneck in VLSI design where RTL-stage PPA (power, performance, area) estimation relies on time-consuming full synthesis—hindering rapid iteration—this paper proposes the first pre-synthesis machine learning framework operating directly on HDL source code. Our method introduces a bit-level Simple Operation Graph (SOG) representation that explicitly models the semantic mapping between RTL constructs and post-synthesis structures. We further design a standard-cell-library-aware tree-based architecture enabling end-to-end PPA prediction solely from Verilog code and library files, without requiring toggle information or synthesis intermediates. Evaluated on 147 industrial-scale RTL designs, our framework achieves 98% accuracy for worst negative slack (WNS), 98% for total negative slack (TNS), and 90% for power estimation—significantly outperforming prior approaches. The method demonstrates strong generalization across diverse designs and high engineering practicality.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Planning, Routing, and Scheduling: Learning for Planning and Scheduling

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking

Abstract

A critical stage in the evolving landscape of VLSI design is the design phase that is transformed into register-transfer level (RTL), which specifies system functionality through hardware description languages like Verilog. Generally, evaluating the quality of an RTL design demands full synthesis via electronic design automation (EDA) tool is time-consuming process that is not well-suited to rapid design iteration and optimization. Although recent breakthroughs in machine Learning (ML) have brought early prediction models, these methods usually do not provide robust and generalizable solutions with respect to a wide range of RTL designs. This paper proposes a pre-synthesis framework that makes early estimation of power, performance and area (PPA) metrics directly from the hardware description language (HDL) code making direct use of library files instead of toggle files. The proposed framework introduces a bit-level representation referred to as the simple operator graph (SOG), which uses single-bit operators to generate a generalized and flexible structure that closely mirrors the characteristics of post synthesis design. The proposed model bridges the RTL and post-synthesis design, which will help in precisely predicting key metrics. The proposed tree-based ML framework shows superior predictive performance PPA estimation. Validation is carried out on 147 distinct RTL designs. The proposed model with 147 different designs shows accuracy of 98%, 98%, and 90% for WNS, TNS and power, respectively, indicates significant accuracy improvements relative to state-of-the-art methods.

Problem

• Early estimation of PPA metrics from HDL code
• Bridging RTL and post-synthesis design for accurate predictions
• Superior predictive performance using tree-based ML framework

Innovation

• Pre-synthesis PPA estimation
• Simple Operator Graph (SOG)
• Tree-based ML framework