Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT

2025-11-17

AI Summary

Large language models (LLMs) face two key challenges in automated IC design: high failure rates in single-shot generation of complex RTL circuits, and poor alignment of conventional chain-of-thought (CoT) reasoning with expert design knowledge and formal verification requirements. Method: We propose VeriBToT, a novel LLM inference paradigm built upon the Backtrack-ToT framework. It integrates three core mechanisms: (1) self-decoupling—decomposing tasks hierarchically by design abstraction; (2) self-verification—embedding formal verification feedback into the reasoning loop; and (3) verifiability-driven tree-of-thought structure—enabling controllable reasoning direction and adjustable step granularity. VeriBToT deeply embeds the Design-for-Verification (DFV) principle into LLM inference, supporting backtracking-based optimization and modular code generation. Contribution/Results: Experiments demonstrate that VeriBToT significantly improves functional correctness and engineering usability of complex Verilog modules, while reducing human intervention frequency and token consumption.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Natural Language Processing: (Large) Language Models

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Search and Retrieval-Augmented AI: Search Tool Learning with LLM: Teaching LLMs to invoke search and make use of retrieved information
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions

Abstract

Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog. However, challenges remain in ensuring the quality of Verilog generation. Complex designs often fail in a single generation due to the lack of targeted decoupling strategies, and evaluating the correctness of decoupled sub-tasks remains difficult. While the chain-of-thought (CoT) method is commonly used to improve LLM reasoning, it has been largely ineffective in automating IC design workflows, requiring manual intervention. The key issue is controlling CoT reasoning direction and step granularity, which do not align with expert RTL design knowledge. This paper introduces VeriBToT, a specialized LLM reasoning paradigm for automated Verilog generation. By integrating Top-down and design-for-verification (DFV) approaches, VeriBToT achieves self-decoupling and self-verification of intermediate steps, constructing a Backtrack Tree of Thought with formal operators. Compared to traditional CoT paradigms, our approach enhances Verilog generation while optimizing token costs through flexible modularity, hierarchy, and reusability.

Problem

• Automating Verilog generation with quality assurance challenges
• Addressing ineffective chain-of-thought in IC design workflows
• Controlling reasoning direction and granularity for RTL design

Innovation

• Self-decoupling strategy for complex Verilog generation
• Self-verification of intermediate design steps
• Backtrack Tree of Thought with formal operators