physical design

This work addresses the limited reproducibility and comparability of machine learning research in electronic design automation (EDA), which stems from the absence of open, standardized datasets. To bridge this gap, the authors propose EDA-Schema-V2—the first standardized multimodal data schema encompassing the full EDA flow from logic synthesis to detailed routing. Leveraging open-source PDKs such as SkyWater 130nm and Nangate 45nm, along with the OpenROAD framework, they generate a large-scale open dataset comprising 7,776 design instances, over 275 million logic gates, and 36 million timing paths through systematic sweeps of process corners, clock periods, and placement parameters. The study defines twelve representative prediction tasks and establishes cross-stage predictability baselines, thereby providing a reproducible benchmark for ML-driven EDA research.

To address the low efficiency in integrated circuit (IC) design stemming from process complexity, frequent iterations, and high reliance on manual intervention, this paper proposes a novel paradigm that deeply integrates large language models (LLMs) into the end-to-end electronic design automation (EDA) flow. Leveraging synergistic modeling of natural language understanding and hardware description language (HDL) code generation, we develop an LLM-driven framework supporting design specification parsing, automated testbench generation, and parameterized optimization. We empirically evaluate the framework on three representative EDA tasks. Results demonstrate substantial reductions in manual effort and accelerated design iteration cycles. Concurrently, the study identifies critical challenges—including semantic gaps between natural and hardware languages, domain-knowledge alignment, and trustworthiness assurance. This work establishes a reproducible technical pathway and delivers systematic insights for the theoretical development and practical deployment of AI-native EDA tools.

This work addresses the challenges in automated PCB schematic design, which are hindered by heterogeneous signal processing, difficulties in modeling realistic IC package constraints, and a lack of open-source datasets and validation methodologies. The authors propose the first training-free framework for automatic schematic generation, integrating large language model agents with constraint-guided synthesis. By leveraging domain-specific prompts, the system iteratively generates circuit code and constructs a knowledge graph derived from IC datasheets to enable precise validation of both topological structure and pin semantics. The approach supports mixed-signal designs encompassing digital, analog, and power circuits, demonstrating significant improvements in design accuracy and computational efficiency across 23 real-world tasks, thereby establishing a novel training-free paradigm for PCB schematic generation.

To address the challenges of PPA (Power-Performance-Area) optimization and poor generalizability of handcrafted features in ultra-large-scale integrated circuit (ULSI) design, this paper proposes the first EDA-oriented multimodal representation learning framework, unifying heterogeneous data—including circuit schematics, rasterized layouts, signal flow graphs, and physical placement maps. Methodologically, we introduce an image–graph hybrid neural architecture that jointly encodes cross-modal data via integrated CNN and GNN modules, enabling effective feature sharing across modalities. Our key contribution lies in overcoming the limitations of conventional feature engineering, supporting end-to-end, multi-task co-optimization for timing prediction, routability analysis, and automated placement. Evaluated on ISCAS and OpenROAD benchmarks, our approach reduces timing prediction error by 32%, improves routing congestion prediction accuracy by 27%, and achieves an average 19% reduction in wirelength (WL/HPWL).

To address low efficiency, insufficient coverage, and poor RTL bug detection in FSM-based chip functional verification, this paper proposes an EDA-feedback-driven, closed-loop LLM testbench generation method. Initial testbenches are generated using GPT-3.5 or GPT-4; then, real-time signal-level feedback—including code and state coverage metrics and error diagnostics—from commercial EDA tools (e.g., Synopsys VCS) is integrated into the prompt engineering process, enabling iterative refinement. This work pioneers deep integration of EDA tool feedback into the LLM generation pipeline, supporting coverage-guided automated test generation and concurrent RTL-level bug detection. Evaluated on multiple industrial-grade FSM designs, the method improves code and state coverage by 20–35% over baseline approaches and successfully identifies timing and control-logic bugs missed by manual verification. The approach significantly enhances both verification efficiency and reliability.

This work addresses the challenge of jointly converging design rule check (DRC) violation repair and power-performance-area (PPA) optimization during electronic design automation (EDA) signoff. To this end, it introduces PostEDA-Bench—the first hierarchical benchmark enabling machine-verifiable evaluation across four key tasks spanning DRC correction and PPA tuning. Notably, this study is the first to integrate DRC repair into an LLM-driven EDA evaluation framework, leveraging vision-augmented large language models (LLMs) coupled with both commercial and open-source EDA toolchains to construct multi-architecture LLM agents for automated reasoning. Experimental results demonstrate that the best-performing agent achieves a 36.66% success rate on the DRC-Reasoning task and 20.00% on the PPA-Multi task, confirming the efficacy of vision enhancement for DRC repair and revealing that the core bottleneck in multi-objective PPA optimization lies in trade-off reasoning capability.

This work addresses the frequent failures of electronic design automation (EDA) code generated by large language models (LLMs), which often arise from violations of implicit structural dependencies among design entities—such as invalid paths, missing preconditions, or API incompatibilities. To overcome the high latency and poor scalability of existing tool-in-the-loop debugging approaches, the authors propose a novel framework for reliable code generation that operates without runtime feedback. The key innovation lies in explicitly modeling structural dependencies as execution contracts and guiding a validator-driven synthesis process via a structural dependency graph. This approach integrates graph-conditioned retrieval, constraint generation, and staged pre-execution validation. Empirical results demonstrate a single-step task pass rate of 82.5%, an improvement in multi-step task success from 30.0% to 84.0%, over twofold reduction in tool invocations, and a validator precision of 93.3% (6.7% false positive rate).

This work addresses the ongoing challenge of automatically translating natural language specifications into editable printed circuit board (PCB) schematics for embedded and IoT development. It presents the first end-to-end approach that leverages tool-augmented large language model reasoning, integrating component library retrieval, datasheet knowledge extraction, execution validation, and structural-semantic verification to generate KiCad-compliant schematics. The system supports iterative refinement through an interactive web interface and achieves a pass@1 rate of 0.90 and a pass@5 rate of 1.00 across 20 embedded schematic generation tasks. This method efficiently produces high-quality initial drafts suitable for early-stage prototype review, substantially advancing the state of hardware design automation.

This work addresses the challenge that existing large language models struggle to simultaneously satisfy stringent geometric, routing, and electrical connectivity constraints in dense PCB layout design. To bridge this gap, we introduce OmniLayout, the first multimodal benchmark specifically tailored for PCB layout, which jointly models schematic diagrams and physical layouts. The benchmark encompasses four constraint-aware reasoning tasks designed to systematically evaluate model capabilities in geometric reasoning, routability, preservation of electrical functionality, and tool invocation. Integrating industrial-scale layout data, geometric constraint modeling, routing analysis, and circuit verification, our framework exposes critical limitations of current models—particularly their weak geometric reasoning, poor routing optimization, and insufficient functional consistency—thereby filling a crucial void in evaluating multimodal collaborative reasoning within electronic design automation.

Congestion in VLSI placement is typically identifiable only after detailed routing, rendering conventional validation workflows time-consuming and costly. This work proposes VeriHGN, a novel framework that for the first time deeply integrates the logical connectivity of circuit netlists with physical placement grids into a unified, enhanced heterogeneous graph representation, overcoming the limitations of prior loosely coupled modeling approaches. Leveraging a heterogeneous graph neural network, the method achieves state-of-the-art performance on industrial benchmarks—including ISPD2015, CircuitNet-N14, and CircuitNet-N28—demonstrating superior accuracy and correlation in early-stage congestion prediction compared to existing techniques.