pcie

To address the challenges of hardware-software co-development and debugging in PCIe-interconnected FPGA systems—including prolonged verification cycles, system instability, and difficulty in error localization—this paper proposes VM-HDL co-simulation, the first virtual machine–HDL co-simulation framework ensuring full-stack consistency. The framework integrates QEMU-based virtualization, SystemC/TLM modeling, a configurable PCIe protocol stack, and a hardware-software time-synchronization mechanism, enabling, for the first time, synchronized debugging and real-time signal observation of OS-level software (including kernel and drivers) alongside RTL hardware. Evaluated on Xilinx Kintex-7 FPGAs running Linux, the framework reduces debugging iteration time by over one order of magnitude, significantly improving development efficiency and system stability. It establishes a new paradigm for high-fidelity, reproducible joint verification of heterogeneous acceleration systems.

This work addresses the high development and deployment costs incurred by maintaining multiple firmware images for GPU servers due to minor hardware variations. To resolve this, the authors propose a unified firmware approach based on runtime hardware identification: during system boot, hardware identity is queried via D-Bus, and a corresponding declarative JSON configuration is dynamically loaded and injected into downstream services as environment variables. This design fully abstracts platform-specific differences into configuration files, eliminating the need for multiple firmware images. Experimental results demonstrate that a single firmware image can efficiently support diverse hardware variants, substantially reducing maintenance complexity and improving deployment efficiency. The core innovation lies in a lightweight, JSON-driven platform abstraction mechanism that integrates seamlessly with the OpenBMC architecture.

This work addresses the fundamental challenge of adapting PCIe SSDs to CXL memory semantics, enabling their use as scalable, byte-addressable working memory. We propose a Type-3 CXL-SSD architecture that implements the CXL 3.0 protocol stack on FPGA and introduces a novel instruction-level semantic annotation mechanism—Determinism and Bufferability—to enable cache behavior control and access determinism while preserving persistence. Integrated with on-die cache co-scheduling, our design achieves tight fusion of storage and memory semantics. Experimental results demonstrate that, compared to PCIe-based memory expanders, our prototype delivers a 10.9× throughput improvement and a 5.4× latency reduction. Under high-locality workloads, its performance approaches that of DRAM. To the best of our knowledge, this is the first SSD-based memory solution for the CXL ecosystem offering simultaneously high performance, rich memory semantics, and strong execution determinism.

To address the challenges of complex PCI device modeling and low simulation performance in SystemC-TLM virtual platforms—hindering efficient early-stage execution and debugging of AI software—this paper proposes a hardware-level native PCI device embedding mechanism. It achieves, for the first time, seamless integration of physical PCIe devices (e.g., Google Coral Edge TPU) into SystemC-TLM-2.0 platforms. Leveraging a lightweight PCIe protocol bridge and hardware-software co-simulation, the approach bypasses conventional virtual device modeling, enabling unmodified AI applications to run natively. Evaluated on an ARM-based virtual platform, it delivers a 480× speedup in AI workload simulation while preserving driver development compatibility and enabling cross-architecture regression testing. This significantly enhances the practicality and productivity of virtual platforms in AI hardware-software co-design.

To address the challenges of assessing non-shortest-path diversity in large-scale interconnection networks and the poor scalability of conventional packet-level simulators, this paper proposes a lightweight simulation framework tailored for extreme-scale networks. By identifying memory and event-scheduling bottlenecks in mainstream simulators, we introduce three core techniques: compact data structures, lazily bound event queues, and lock-free memory pools—significantly reducing both memory footprint and synchronization overhead. Our framework enables fine-grained, packet-level simulation of data center and HPC networks with over one million endpoints on a single commodity laptop, achieving a throughput of 10 million packets per second—three orders of magnitude higher than state-of-the-art shared-memory simulators. The open-source framework supports rapid prototyping and validation of novel interconnect protocols, providing a reproducible, high-fidelity foundation for path diversity analysis and performance optimization in ultra-large-scale networks.

This work addresses the challenges of scaling distributed AI training to hundreds of thousands of GPUs, where conventional networks struggle to simultaneously achieve high throughput, low latency, and stability under dynamic loads. The authors propose Spectrum-X, a multi-plane network architecture that replaces hierarchical topologies with topological parallelism and integrates hardware-accelerated load balancing directly into NICs and switches. This design enables microsecond-scale link-state awareness and response, co-optimizing multi-plane topology and hardware-level scheduling to significantly enhance bandwidth utilization and fault resilience. Experimental results demonstrate that the system achieves 98% line-rate throughput with near-zero jitter, incurs only a 7% latency increase under 10% link failures, and supports strong multi-tenant isolation—effectively meeting the stringent communication demands of large-scale model training.

This work addresses the non-uniform effective resistance distribution and severe IR drop in 3D IC power delivery networks caused by suboptimal through-silicon via (TSV) placement. To enable rapid assessment of TSV layout impact on power integrity during early design stages, the authors propose a GPU-accelerated effective resistance analysis framework. Leveraging highly efficient GPU-parallelized numerical solvers as a replacement for conventional direct solvers, the method achieves a speedup of five to six orders of magnitude while maintaining exceptionally low maximum and average relative errors. Compared to traditional approaches, the proposed framework enhances analysis throughput by 10⁵–10⁶ times without compromising accuracy, thereby significantly improving the efficiency and scalability of early-stage verification for complex 3D IC power networks.

This work addresses the lack of transparency in NVIDIA’s closed-source user-space driver, which obscures the translation of CUDA API calls into hardware commands and impedes understanding of GPU behavior and performance attribution. The authors propose a novel approach that requires no modification to the proprietary driver, instead leveraging an open-source kernel driver, memory-mapped path instrumentation, and hardware watchpoints on the GPU’s doorbell registers to capture and reconstruct the complete low-level command stream with unprecedented accuracy. This methodology reveals the true DMA patterns and performance characteristics of CUDA data transfers and demonstrates that the low overhead of CUDA Graphs stems from their streamlined and efficient command submission mechanism. By significantly enhancing the interpretability of GPU runtime behavior, this approach establishes a new paradigm for middleware analysis and hardware-software co-design.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This study addresses the severe performance degradation of collective communication in modern high-performance computing (HPC) interconnects caused by network congestion induced by heterogeneous workloads. It presents the first systematic evaluation of EDR/HDR/NDR InfiniBand, Cray Slingshot, and emerging Ethernet interconnects under both steady-state and bursty congestion across multiple system scales and diverse burst patterns. Through controlled experiments on real HPC platforms, the authors emulate bursts of varying intensity, duration, and interval, combined with collective communication microbenchmarks, to uncover the scale-dependent nature of congestion behavior and its relationship to typical AI communication patterns. The findings delineate distinct performance degradation characteristics across interconnect technologies, providing critical empirical insights for designing effective congestion control and load-balancing strategies.