A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs

2017-08-16

AI Summary

To address the challenges of hardware-software co-development and debugging in PCIe-interconnected FPGA systems—including prolonged verification cycles, system instability, and difficulty in error localization—this paper proposes VM-HDL co-simulation, the first virtual machine–HDL co-simulation framework ensuring full-stack consistency. The framework integrates QEMU-based virtualization, SystemC/TLM modeling, a configurable PCIe protocol stack, and a hardware-software time-synchronization mechanism, enabling, for the first time, synchronized debugging and real-time signal observation of OS-level software (including kernel and drivers) alongside RTL hardware. Evaluated on Xilinx Kintex-7 FPGAs running Linux, the framework reduces debugging iteration time by over one order of magnitude, significantly improving development efficiency and system stability. It establishes a new paradigm for high-fidelity, reproducible joint verification of heterogeneous acceleration systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Conceptual Inference and Reasoning
• Computer Vision: Low Level & Physics-based Vision

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems
• Web Mining and Content Analysis: Web data generation and simulation

Abstract

PCIe-connected FPGAs are gaining popularity as an accelerator technology in data centers. However, it is challenging to jointly develop and debug host software and FPGA hardware. Changes to the hardware design require a time-consuming FPGA synthesis process, and modification to the software, especially the operating system and device drivers, can frequently cause the system to hang, without providing enough information for debugging. The combination of these problems results in long debug iterations and a slow development process. To overcome these problems, we designed a VM-HDL co-simulation framework, which is capable of running the same software, operating system, and hardware designs as the target physical system, while providing full visibility and significantly shorter debug iterations.

Problem

• FPGA Acceleration
• Software-Hardware Co-development
• Error Detection

Innovation

• VM-HDL Co-Simulation
• PCIe-connected FPGA
• Debugging Efficiency