computer hardware and architecture

Hardware description language (HDL) understanding—particularly for VHDL in high-performance microprocessor design—lacks effective AI support. Method: This paper proposes a large language model (LLM) customization framework specifically for HDLs. Its core innovations include: (1) a novel VHDL-specific Extended Pre-Training (EPT) paradigm to enhance modeling of hardware semantics such as sequential logic and parallel constructs; (2) an LLM-as-a-judge automated evaluation framework achieving high agreement with human experts (Spearman’s ρ = 0.92); and (3) a domain-adapted benchmark suite and expert-aligned evaluation protocol. Results: Experiments show EPT improves expert-assessed accuracy from a baseline of 43% to 69%; instruction fine-tuning further raises it to 71%, with projections exceeding 85% on a newly initialized base model—significantly bridging the technical gap in intelligent VHDL comprehension.

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

The absence of a systematic survey on large language models (LLMs) for Verilog RTL code generation hinders progress in hardware-AI co-design. Method: This paper conducts a cross-domain (software engineering/AI/EDA) analysis of 102 publications—70 peer-reviewed papers and 32 high-quality preprints—using bibliometric analysis, topic modeling, and cross-domain comparison, complemented by evaluation techniques including fine-tuning, prompt engineering, and functional correctness assessment. Contribution/Results: We introduce the first LLM-Verilog research map and a four-dimensional analytical framework addressing key research questions. Core bottlenecks are identified: architectural limitations of LLMs, scarcity of high-quality Verilog training data, and insufficient functional correctness guarantees. Furthermore, we propose a novel three-stage roadmap—“verifiable generation → hardware-aware alignment → EDA toolchain integration”—to guide future development, offering both theoretical foundations and practical pathways for LLM-driven RTL synthesis.

Large language models (LLMs) face two key challenges in automated IC design: high failure rates in single-shot generation of complex RTL circuits, and poor alignment of conventional chain-of-thought (CoT) reasoning with expert design knowledge and formal verification requirements. Method: We propose VeriBToT, a novel LLM inference paradigm built upon the Backtrack-ToT framework. It integrates three core mechanisms: (1) self-decoupling—decomposing tasks hierarchically by design abstraction; (2) self-verification—embedding formal verification feedback into the reasoning loop; and (3) verifiability-driven tree-of-thought structure—enabling controllable reasoning direction and adjustable step granularity. VeriBToT deeply embeds the Design-for-Verification (DFV) principle into LLM inference, supporting backtracking-based optimization and modular code generation. Contribution/Results: Experiments demonstrate that VeriBToT significantly improves functional correctness and engineering usability of complex Verilog modules, while reducing human intervention frequency and token consumption.

This work addresses the limited generalization capability of large language models (LLMs) across hardware description languages, particularly due to the absence of a systematic evaluation framework for VHDL. We propose the first unified framework for LLM-based VHDL generation and evaluation, introducing an automated, verifiable Verilog-to-VHDL benchmark conversion pipeline. The resulting VHDLBench dataset comprises over 200 VHDL modules, each accompanied by complete testbenches. Integrating automated data synthesis, the VUnit/GHDL verification toolchain, and multi-model comparative analysis, our framework enables the first comprehensive assessment of LLM-generated VHDL code in terms of compilability, executability, and functional correctness. This study reveals critical challenges posed by VHDL-specific semantics and structural constructs, laying the groundwork for multilingual hardware design automation.

This work addresses the challenges large language models face in generating synthesizable Verilog for hierarchical hardware designs, where inconsistent interfaces and fragmented structural context often lead to hallucinated wiring and loss of contextual coherence. To overcome these issues, the authors propose VeriGraphi, a novel framework that introduces, for the first time, a specification-anchored Hierarchical Design Anchor (HDA) knowledge graph as a structured intermediate representation. This graph explicitly models module hierarchy, port interfaces, wiring semantics, and dependency relationships. Leveraging a multi-agent collaborative approach, VeriGraphi enables progressive generation of pseudocode and Verilog code. Evaluated on NIST specifications and an RV32I processor case study, the method significantly improves functional correctness, reduces manual intervention, and achieves high-fidelity automated generation of hierarchical RTL.

Reproducing hardware architectures from academic papers remains challenging due to missing source code and the inherent complexity of hardware description languages (HDLs). To address this, we propose a neuro-symbolic graph framework that enables end-to-end generation of synthesizable Verilog RTL and corresponding verification environments directly from unstructured architectural text. Our approach formalizes architectural blueprints as graphs and encodes functional specifications via symbolic rules, jointly generating RTL modules and testbenches while integrating synthesis, timing analysis, and PPA (power-performance-area) evaluation. We introduce ArchSynthBench—the first architecture-to-hardware synthesis benchmark—comprising 50 system-level circuits and 600 modules, and decouple design and verification to enhance correctness and debuggability. Experiments show that all generated RTL meets timing constraints, matches original performance metrics, and achieves higher code completion and architectural understanding accuracy than state-of-the-art baselines (e.g., VerilogCoder).

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

This work addresses the challenge of efficiently verifying large-scale RTL designs generated by high-level synthesis (HLS), which often overwhelm conventional model checking techniques. The authors propose a novel method that leverages high-level semantic information from HLS to automatically generate guided invariants, which augment assertions to accelerate formal verification. A proof-guided selection mechanism is introduced to iteratively refine and identify an optimal set of assertions. This approach represents the first systematic integration of HLS-level features into automated invariant generation, substantially improving verification efficiency. Experimental results across multiple HLS benchmarks demonstrate an average speedup of 2.23×, with a maximum acceleration of 6.05× compared to baseline methods.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.