Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead

2025-10-29

AI Summary

The absence of a systematic survey on large language models (LLMs) for Verilog RTL code generation hinders progress in hardware-AI co-design. Method: This paper conducts a cross-domain (software engineering/AI/EDA) analysis of 102 publications—70 peer-reviewed papers and 32 high-quality preprints—using bibliometric analysis, topic modeling, and cross-domain comparison, complemented by evaluation techniques including fine-tuning, prompt engineering, and functional correctness assessment. Contribution/Results: We introduce the first LLM-Verilog research map and a four-dimensional analytical framework addressing key research questions. Core bottlenecks are identified: architectural limitations of LLMs, scarcity of high-quality Verilog training data, and insufficient functional correctness guarantees. Furthermore, we propose a novel three-stage roadmap—“verifiable generation → hardware-aware alignment → EDA toolchain integration”—to guide future development, offering both theoretical foundations and practical pathways for LLM-driven RTL synthesis.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation

Abstract

Code generation has emerged as a critical research area at the intersection of Software Engineering (SE) and Artificial Intelligence (AI), attracting significant attention from both academia and industry. Within this broader landscape, Verilog, as a representative hardware description language (HDL), plays a fundamental role in digital circuit design and verification, making its automated generation particularly significant for Electronic Design Automation (EDA). Consequently, recent research has increasingly focused on applying Large Language Models (LLMs) to Verilog code generation, particularly at the Register Transfer Level (RTL), exploring how these AI-driven techniques can be effectively integrated into hardware design workflows. Despite substantial research efforts have explored LLM applications in this domain, a comprehensive survey synthesizing these developments remains absent from the literature. This review fill addresses this gap by providing a systematic literature review of LLM-based methods for Verilog code generation, examining their effectiveness, limitations, and potential for advancing automated hardware design. The review encompasses research work from conferences and journals in the fields of SE, AI, and EDA, encompassing 70 papers published on venues, along with 32 high-quality preprint papers, bringing the total to 102 papers. By answering four key research questions, we aim to (1) identify the LLMs used for Verilog generation, (2) examine the datasets and metrics employed in evaluation, (3) categorize the techniques proposed for Verilog generation, and (4) analyze LLM alignment approaches for Verilog generation. Based on our findings, we have identified a series of limitations of existing studies. Finally, we have outlined a roadmap highlighting potential opportunities for future research endeavors in LLM-assisted hardware design.

Problem

• Surveying LLM applications for automated Verilog code generation
• Analyzing effectiveness and limitations of AI-driven hardware design methods
• Providing roadmap for future LLM-assisted electronic design automation

Innovation

• Systematic review of LLM-based Verilog generation methods
• Analysis of techniques and alignment approaches for hardware design
• Roadmap for future LLM-assisted automated hardware design