About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Drive the complete RTL life-cycle from initial microarchitecture, coding, and documentation to sign-off readiness (Lint, CDC, synthesis) for high-performance designs meeting strict PPA targets and quality guidelines.
Collaborate with system architects to align on chip-level bandwidth, latency, and power objectives, and partner with the Verification and Physical Design teams to define test plans and achieve timing closure.
Identify test requirements, define methodology/tools, and execute testing of silicon systems; drive protocol resolution and lead post-silicon bring-up to validate link integrity and subsystem performance.
Influence designs to enhance testing, validation, and debugging capabilities, while establishing third-party IP requirements and driving the selection process.
Develop and maintain policies, processes, procedures, methods, and documentation for silicon deliverables to enhance efficiency, productivity, and project sustainability.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with three or more SoC projects/cycles.
Familiarity with the full ASIC flow (DFT, synthesis, PnR), SerDes behavior, and scripting (Python, Tcl, or Perl) to drive technical execution.
Expert knowledge of NoC/Memory architecture, flow control, and performance tuning.
Proven ability to lead cross-functional efforts with software and system hardware teams, from initial library RTL development through to silicon bring-up.
Advanced RTL design skills with mastery of multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.