Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework

2025-11-08

AI Summary

Reproducing hardware architectures from academic papers remains challenging due to missing source code and the inherent complexity of hardware description languages (HDLs). To address this, we propose a neuro-symbolic graph framework that enables end-to-end generation of synthesizable Verilog RTL and corresponding verification environments directly from unstructured architectural text. Our approach formalizes architectural blueprints as graphs and encodes functional specifications via symbolic rules, jointly generating RTL modules and testbenches while integrating synthesis, timing analysis, and PPA (power-performance-area) evaluation. We introduce ArchSynthBench—the first architecture-to-hardware synthesis benchmark—comprising 50 system-level circuits and 600 modules, and decouple design and verification to enhance correctness and debuggability. Experiments show that all generated RTL meets timing constraints, matches original performance metrics, and achieves higher code completion and architectural understanding accuracy than state-of-the-art baselines (e.g., VerilogCoder).

Technology Category

• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Machine Learning: Deep Neural Architectures and Foundation Models

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

The reproduction of hardware architectures from academic papers remains a significant challenge due to the lack of publicly available source code and the complexity of hardware description languages (HDLs). To this end, we propose extbf{ArchCraft}, a Framework that converts abstract architectural descriptions from academic papers into synthesizable Verilog projects with register-transfer level (RTL) verification. ArchCraft introduces a structured workflow, which uses formal graphs to capture the Architectural Blueprint and symbols to define the Functional Specification, translating unstructured academic papers into verifiable, hardware-aware designs. The framework then generates RTL and testbench (TB) code decoupled via these symbols to facilitate verification and debugging, ultimately reporting the circuit's Power, Area, and Performance (PPA). Moreover, we propose the first benchmark, extbf{ArchSynthBench}, for synthesizing hardware from architectural descriptions, with a complete set of evaluation indicators, 50 project-level circuits, and around 600 circuit blocks. We systematically assess ArchCraft on ArchSynthBench, where the experiment results demonstrate the superiority of our proposed method, surpassing direct generation methods and the VerilogCoder framework in both paper understanding and code completion. Furthermore, evaluation and physical implementation of the generated executable RTL code show that these implementations meet all timing constraints without violations, and their performance metrics are consistent with those reported in the original papers.

Problem

• Automates hardware design from academic papers using neural-symbolic graphs
• Generates synthesizable Verilog code with RTL verification capabilities
• Creates benchmark for evaluating architectural description synthesis methods

Innovation

• Neural-symbolic graph framework automates hardware design
• Generates synthesizable Verilog code with RTL verification
• Creates benchmark for evaluating architectural synthesis methods