About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Perform physical design of blocks from register-transfer level (RTL) to graphic data system (GDS).
Use problem-solving, debugging skills and collaborate cross-functional teams to achieve the best power/performance analysis (PPA).
Develop, validate, and improve electronic design automation (EDA) methodology for a specialized implementation and sign-off domains.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with physical design from RTL to GDSII, including synthesis, floor planning, place and route, and timing closure.
Experience with scripting languages in one or more of the following: Perl, Python, or Tcl.
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in floor planning, block integration, static timing analysis, sign-off.
Experience executing low-power physical design implementation using industry-standard EDA tools (Innovus/FC).
Experience in utilizing AI techniques for faster and optimal physical design convergence (e.g., timing, floorplanning, power grid, and clock tree design).
Experience in sign-off convergence including static timing analysis (STA), electrical checks, and physical verification.