Unifying Logical and Physical Layout Representations via Heterogeneous Graphs for Circuit Congestion Prediction

2026-03-10

AI Summary

Congestion in VLSI placement is typically identifiable only after detailed routing, rendering conventional validation workflows time-consuming and costly. This work proposes VeriHGN, a novel framework that for the first time deeply integrates the logical connectivity of circuit netlists with physical placement grids into a unified, enhanced heterogeneous graph representation, overcoming the limitations of prior loosely coupled modeling approaches. Leveraging a heterogeneous graph neural network, the method achieves state-of-the-art performance on industrial benchmarks—including ISPD2015, CircuitNet-N14, and CircuitNet-N28—demonstrating superior accuracy and correlation in early-stage congestion prediction compared to existing techniques.

Technology Category

• Machine Learning: Graph-based Machine Learning
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.

Problem

• circuit congestion prediction
• VLSI design
• layout verification
• Electronic Design Automation
• early-stage prediction

Innovation

• heterogeneous graph
• congestion prediction
• layout verification
• VLSI design
• unified representation