CPPL: A Circuit Prompt Programming Language

2026-05-18

AI Summary

This work addresses the challenges of directly generating RTL code with large language models (LLMs), which often suffer from verification difficulties, limited optimizability, and poor integration with compiler-driven design flows. To overcome these issues, the authors propose the CPPL framework, which introduces a compiler-mediated interface for the first time. By leveraging a Python-based frontend DSL and a JSON-encoded CPPL intermediate representation (IR), the approach reframes LLM-assisted hardware generation as a statically checkable frontend problem. The framework exploits the CIRCT infrastructure to automatically infer bit widths, validate structural correctness, and lower designs to synthesizable Verilog. This ensures generated circuits are type-safe, hierarchically structured, verifiable, and amenable to optimization. Evaluated on the RTLLM benchmark, the method significantly improves functional correctness and, after CIRCT-based optimization, yields synthesized circuits with substantially fewer AIG nodes.

Abstract

Large language models (LLMs) have shown promise in register-transfer level (RTL) design automation, but direct RTL generation remains difficult to validate, optimize, and integrate with compiler-based hardware design flows. Hardware compiler infrastructures such as CIRCT provide typed intermediate representations, legality checks, and optimization passes, yet current LLMs struggle to emit raw compiler IR because of MLIR syntax, SSA discipline, dialect-specific operations, and strict width constraints. This paper presents CPPL, a compiler-mediated design framework that turns LLM-assisted hardware generation into a statically checkable frontend problem rather than an unconstrained RTL text-generation task. CPPL combines a Python frontend DSL for declaring module interfaces and hierarchy with CPPL IR, a JSON-based circuit IR designed to expose compiler-visible structure while remaining accessible to LLMs. The compiler infers operation widths from declared module ports, validates generated IR, checks hierarchy and port bindings, and deterministically lowers the result to CIRCT for synthesizable Verilog generation. On the RTLLM benchmark, CPPL improves functional correctness over direct Verilog and direct CIRCT IR generation, while CIRCT optimization reduces post-synthesis AIG node counts. These results show that a compiler-mediated interface can make LLM-assisted hardware design more reliable, analyzable, and amenable to backend optimization. CPPL is available at https://github.com/SawyDust1228/CPPL.

Problem

• LLM-assisted hardware design
• RTL generation
• compiler IR
• hardware compilation
• design automation

Innovation

• CPPL
• LLM-assisted hardware design
• compiler-mediated framework
• CIRCT
• intermediate representation