About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Help own, maintain and upgrade our emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team and implement new emulation workflows and methodologies.
Support emulation team members in debug of hardware, tooling, and project specific issues, as well as software team members in running and debugging tests and performing functional validation on emulation platforms.
Bring up external interfaces (e.g., Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), or Ethernet on the emulation platforms and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
Experience with coding or scripting in C, C++, Perl, TCL or Python.
Experience with emulation systems (e.g., ZeBu, Palladium, Veloce), compilation, debugging, performance and methodology enhancements.
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
Experience with performance analysis/debug techniques.
Knowledge of external input/output (I/O) interfaces, such as Peripheral Component Interconnect Express (PCIe), Double Data Rate 5 (DDR5), High Bandwidth Memory (HBM), Serial Peripheral Interface (SPI), or Joint Test Action Group (JTAG).
Understanding of computer architecture including industry standard interfaces and memory subsystems.