Information Flow Paths from RTL Traces

2026-06-11

AI Summary

This work proposes a novel approach to hardware security verification by automatically constructing end-to-end information flow paths from register transfer level (RTL) trace data. Unlike conventional information flow analyses that merely detect whether data flows between registers, the proposed method reconstructs complete propagation pathways of sensitive information at the RTL trace level for the first time. By integrating information flow tracking with specification mining techniques, the framework automatically generates and verifies security properties. This paradigm overcomes the limitations of pairwise flow detection, substantially enhancing the automation, precision in violation detection, and efficiency of system-wide security evaluation in hardware designs.

Abstract

Security validation is an important yet challenging part of the hardware design process, yet, by convention, validation engineers are tasked with defining the threat model, specifying the relevant security properties, detecting any violations of those properties, and assessing the consequences to system security, each of which is manually intensive and may introduce errors. The combined technologies of information flow tracking and specification mining represent an automated approach to property generation and validation, but prior work on information flow tracking on RTL trace data was limited to find cases under which information flowed between registers, without reproducing full paths to capture how sensitive information propagates through a design. With the introduction of new technologies accelerating hardware analysis, we develop a novel approach for constructing information flow paths from register transfer level (RTL) trace data.

Problem

• information flow
• RTL trace
• security validation
• hardware design
• path reconstruction

Innovation

• information flow tracking
• RTL trace analysis
• security validation
• specification mining
• hardware security