About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Lead the RTL design and implementation of high-speed blocks.
Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.
Transform high-level architectural specifications and communication theory models into efficient, bit-exact SystemVerilog/Verilog implementations.
Perform fixed-point analysis and micro-architectural trade-offs to optimize for area, power, and performance.
Drive the front-end design flow, including synthesis, Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalency Checking (LEC) to ensure robust, sign-off quality designs.
Collaborate closely with verification teams to develop bit-exact C++/SystemC models and UVM environments for comprehensive RTL verification.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
10 years of experience in design for Digital Signal Processing (DSP) or high-speed digital logic.
Experience in Verilog/SystemVerilog or VHDL.
Experience with MATLAB, Python, or C++ for algorithmic modeling and verification.
Preferred
Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
Experience taking complex DSP designs through the full front-end flow: Synthesis (Design Compiler/Genus), STA (PrimeTime/Tempus), and CDC/LEC (Spyglass/Conformal).
Experience implementing digital blocks for Communication Systems or PHY (e.g., filters, interpolators, or equalizers).
Experience with advanced FinFET process nodes (e.g., 5nm, 3nm) and achieving timing closure at GHz frequencies.
Understanding of low-power design techniques and dynamic power optimization.