Jiaping Tang
Scholar

Jiaping Tang

Google Scholar ID: oVGfLp8AAAAJ
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences
RTL SimulationAutomatic RTL DebugSoftware/Hardware co-acceleration
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Citations & Impact
All-time
Citations
7
 
H-index
1
 
i10-index
0
 
Publications
6
 
Co-authors
5
list available
Contact
No contact links provided.
Publications
5 items
ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression
2026
Cited
0
Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction
2026
Cited
0
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule
2025
Cited
0
Extend IVerilog to Support Batch RTL Fault Simulation
2025
Cited
0
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
2025
Cited
0
Resume (English only)
Co-authors
5 total
Jianan Mu
Jianan Mu
Institute of Computing Technology, State Key Laboratory of Processors (SKLP), CAS
Xiaowei Li (李晓维)
Xiaowei Li (李晓维)
Institute of Computing Technology, Chinese Academy of Sciences
Co-author 3
Co-author 3
Huawei Li
Huawei Li
Institute of Computing Technology, Chinese Academy of Sciences
Zhiteng Chao
Zhiteng Chao
SKLP, ICT