Extend IVerilog to Support Batch RTL Fault Simulation

2025-05-10

AI Summary

To address the low efficiency of RTL-level fault simulation in functional safety verification, this paper proposes a batch fault simulation extension method based on IVerilog. It introduces, for the first time in an open-source Verilog simulator, an event-driven simulation mechanism integrated with a lightweight concurrent fault injection algorithm, and designs a batch stimulus scheduling strategy to enable high-throughput, low-overhead parallel fault simulation. Compared with commercial tools (e.g., VCS) and mainstream open-source alternatives (e.g., Icarus Verilog), the proposed method achieves 2.2× and 3.4× simulation speedup, respectively, under identical test stimuli. This significantly reduces fault coverage convergence time, accelerates early design iteration, and enhances compliance verification capability with functional safety standards such as ISO 26262.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Cognitive Modeling & Cognitive Systems: Simulating Human Behavior
• Planning, Routing, and Scheduling: Replanning and Plan Repair

Application Category

• Security and Privacy: Large-scale security measurements
• Web Mining and Content Analysis: Web data generation and simulation
• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems

Abstract

The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure compliance with functional safety standards. In this paper, we extend IVerilog to support batch RTL fault simulation and integrate the event-driven algorithm and the concurrent fault simulation algorithm. Comparative experiments with a state-of-the-art commercial simulator and an open-source RTL fault simulator demonstrate that our simulator achieves a performance improvement of 2.2$ imes$ and 3.4$ imes$, respectively.

Problem

• Extend IVerilog for batch RTL fault simulation
• Integrate event-driven and concurrent fault algorithms
• Improve simulation performance over existing tools

Innovation

• Extend IVerilog for batch RTL fault simulation
• Integrate event-driven and concurrent fault algorithms
• Achieve 2.2-3.4x performance improvement over competitors