ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy

2025-04-23

AI Summary

In RTL fault simulation, redundant executions of behavioral nodes (e.g., `always` blocks) severely impede efficiency. Existing approaches detect redundancy solely based on input consistency, overlooking pervasive “implicit redundancy”—scenarios where faulty and fault-free inputs differ, yet the executed control paths and output values remain identical; such cases account for nearly 50% of behavioral node overhead. This work introduces, for the first time, a behavioral-level redundancy detection algorithm grounded in actual execution paths. It dynamically identifies and prunes redundant paths, employs lightweight fault modeling, and restructures the RTL simulation flow to transcend conventional input-based redundancy criteria. Experimental evaluation demonstrates that, under equivalent fault coverage, the proposed method achieves an average 3.9× speedup over baseline simulation—substantially outperforming state-of-the-art commercial tools.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning
• Reasoning under Uncertainty: Other Foundations of Reasoning under Uncertainty

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web
• Security and Privacy: Large-scale security measurements

Abstract

As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric for functional safety is achieving a sufficient fault coverage. To meet this requirement, extensive time-consuming fault simulation of the RTL code is necessary during the chip design phase.The main overhead in RTL fault simulation comes from simulating behavioral nodes (always blocks). Due to the limited fault propagation capacity, fault simulation results often match the good simulation results for many behavioral nodes. A key strategy for accelerating RTL fault simulation is the identification and elimination of redundant simulations. Existing methods detect redundant executions by examining whether the fault inputs to each RTL node are consistent with the good inputs. However, we observe that this input comparison mechanism overlooks a significant amount of implicit redundant execution: although the fault inputs differ from the good inputs, the node's execution results remain unchanged. Our experiments reveal that this overlooked redundant execution constitutes nearly half of the total execution overhead of behavioral nodes, becoming a significant bottleneck in current RTL fault simulation. The underlying reason for this overlooked redundancy is that, in these cases, the true execution paths within the behavioral nodes are not affected by the changes in input values. In this work, we propose a behavior-level redundancy detection algorithm that focuses on the true execution paths. Building on the elimination of redundant executions, we further developed an efficient RTL fault simulation framework, Eraser.Experimental results show that compared to commercial tools, under the same fault coverage, our framework achieves a 3.9 $ imes$ improvement in simulation performance on average.

Problem

• Reducing RTL fault simulation time by eliminating redundant executions
• Identifying implicit redundant executions in behavioral nodes
• Improving fault simulation performance while maintaining coverage

Innovation

• Behavior-level redundancy detection algorithm
• Focuses on true execution paths
• Eliminates redundant RTL fault simulations