RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule

2025-08-22

AI Summary

Parallel efficiency in RTL-level fault simulation for safety-critical chips (e.g., autonomous driving, embodied AI) is severely hindered by dynamic fault propagation paths and highly imbalanced task loads. Method: This paper proposes a two-dimensional parallel architecture integrating structural-level parallelism (with work-stealing) and fault-level parallelism, coupled with a unified compute/global-synchronization scheduling mechanism to eliminate simulation bubbles. The approach fundamentally restructures the conventional serial execution and synchronous paradigm, enabling both high throughput for lightweight tasks and fine-grained decomposition for heavy-load tasks. Contribution/Results: Experimental evaluation demonstrates speedups of 7.0× over the state-of-the-art academic RTL fault simulator and 11.0× over leading commercial tools, significantly reducing verification turnaround time and enabling scalable functional safety compliance verification.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Replanning and Plan Repair

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

With the rapid development of safety-critical applications such as autonomous driving and embodied intelligence, the functional safety of the corresponding electronic chips becomes more critical. Ensuring chip functional safety requires performing a large number of time-consuming RTL fault simulations during the design phase, significantly increasing the verification cycle. To meet time-to-market demands while ensuring thorough chip verification, parallel acceleration of RTL fault simulation is necessary. Due to the dynamic nature of fault propagation paths and varying fault propagation capabilities, task loads in RTL fault simulation are highly imbalanced, making traditional singledimension parallel methods, such as structural-level parallelism, ineffective. Through an analysis of fault propagation paths and task loads, we identify two types of tasks in RTL fault simulation: tasks that are few in number but high in load, and tasks that are numerous but low in load. Based on this insight, we propose a two-dimensional parallel approach that combines structurallevel and fault-level parallelism to minimize bubbles in RTL fault simulation. Structural-level parallelism combining with workstealing mechanism is used to handle the numerous low-load tasks, while fault-level parallelism is applied to split the high-load tasks. Besides, we deviate from the traditional serial execution model of computation and global synchronization in RTL simulation by proposing a unified computation/global synchronization scheduling approach, which further eliminates bubbles. Finally, we implemented a parallel RTL fault simulation framework, RIROS. Experimental results show a performance improvement of 7.0 times and 11.0 times compared to the state-of-the-art RTL fault simulation and a commercial tool.

Problem

• Accelerating RTL fault simulation for chip functional safety
• Addressing task load imbalance in parallel fault simulation
• Reducing verification cycle time with two-dimensional parallelism

Innovation

• Two-dimensional parallelism combining structural and fault levels
• Work-stealing mechanism for load balancing
• Unified computation and global synchronization scheduling