Selected work

Representative Papers

Porting and Benchmarking Chapel on Emerging RISC-V Hardware: an HPC Viability Study

Aug 14, 2026

This study addresses the need to evaluate RISC-V’s suitability for high-performance computing (HPC) by presenting the first systematic port of the Chapel programming language to this platform. Leveraging standard HPC benchmark suites, we conduct a comprehensive cross-platform performance comparison that successfully validates Chapel’s adaptability on RISC-V while identifying critical performance anomalies and bottlenecks inherent in cross-architecture migration. The results demonstrate that RISC-V possesses the technical potential to support future HPC workloads effectively. Consequently, this work provides empirical evidence and methodological guidance for integrating emerging instruction set architectures into the broader HPC ecosystem, establishing a foundational baseline for subsequent research and development in this domain.

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WaveformQA: Benchmarking LLM Temporal Reasoning on Digital Waveforms

Jul 22, 2026

This work addresses the lack of systematic evaluation of large language models’ (LLMs’) temporal reasoning capabilities on digital waveforms, as existing benchmarks predominantly focus on hardware description language generation while neglecting complex timing and multi-signal relational reasoning. To bridge this gap, we introduce WaveformQA—an open-source question-answering benchmark comprising 360 programmatically generated questions derived from real-world open-source hardware designs, spanning eight progressively challenging temporal reasoning tasks. We innovatively replace conventional VCD waveform representations with an event-time JSON format, which substantially improves LLM inference accuracy and enables a standardized evaluation framework. Experimental results demonstrate that state-of-the-art LLMs perform adequately on simple queries but exhibit significant limitations in complex, multi-step or multi-signal scenarios; our proposed JSON representation effectively alleviates context-length and parsing bottlenecks, facilitating flexible extension to diverse question types and waveform sources.

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CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems

Jun 24, 2026

This work addresses the challenges of uncontrolled worst-case processor latency and highly variable task execution times in mixed-criticality systems by introducing, for the first time, three real-time microarchitectural enhancements to the open-source CVA6 (RV64GC) processor. These include a TLB with partition locking support, a dynamically reconfigurable scratchpad mode for the L1 cache, and an enhanced interrupt controller featuring hardware-assisted context stacking. Together, these mechanisms ensure deterministic memory access and substantially reduce interrupt response latency. Experimental results demonstrate that with these real-time features enabled, interrupt latency is reduced to 12 cycles—tenfold lower than that of the baseline CVA6—achieving timing predictability comparable to Arm Cortex-M class processors.

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Exploring Fast Fourier Transforms on the Tenstorrent Wormhole

Jun 18, 2025

RISC-V’s adoption in high-performance computing (HPC) remains limited due to a lack of optimized domain-specific workloads. Method: This paper presents the first implementation and deep optimization of 2D Fast Fourier Transform (FFT) on the Tenstorrent Wormhole n300 PCIe accelerator—built upon the RISC-V-based Tensix architecture—leveraging its decoupled compute and data movement hardware to address memory bandwidth bottlenecks via customized optimizations, including memory access reordering and tiling. Numerical accuracy is strictly preserved. Contribution/Results: Experiments show that Wormhole n300 achieves ~8× lower power consumption and 2.8× lower energy consumption than a 24-core Intel Xeon Platinum CPU for 2D FFT. This work demonstrates the practical viability of RISC-V-based accelerators in energy-constrained HPC scenarios and establishes a reusable algorithm-architecture co-design methodology for open instruction set architectures in scientific computing.

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Recent publications

Latest Papers

Porting and Benchmarking Chapel on Emerging RISC-V Hardware: an HPC Viability Study

Aug 14, 2026

This study addresses the need to evaluate RISC-V’s suitability for high-performance computing (HPC) by presenting the first systematic port of the Chapel programming language to this platform. Leveraging standard HPC benchmark suites, we conduct a comprehensive cross-platform performance comparison that successfully validates Chapel’s adaptability on RISC-V while identifying critical performance anomalies and bottlenecks inherent in cross-architecture migration. The results demonstrate that RISC-V possesses the technical potential to support future HPC workloads effectively. Consequently, this work provides empirical evidence and methodological guidance for integrating emerging instruction set architectures into the broader HPC ecosystem, establishing a foundational baseline for subsequent research and development in this domain.

0 citationsRead paper

WaveformQA: Benchmarking LLM Temporal Reasoning on Digital Waveforms

Jul 22, 2026

This work addresses the lack of systematic evaluation of large language models’ (LLMs’) temporal reasoning capabilities on digital waveforms, as existing benchmarks predominantly focus on hardware description language generation while neglecting complex timing and multi-signal relational reasoning. To bridge this gap, we introduce WaveformQA—an open-source question-answering benchmark comprising 360 programmatically generated questions derived from real-world open-source hardware designs, spanning eight progressively challenging temporal reasoning tasks. We innovatively replace conventional VCD waveform representations with an event-time JSON format, which substantially improves LLM inference accuracy and enables a standardized evaluation framework. Experimental results demonstrate that state-of-the-art LLMs perform adequately on simple queries but exhibit significant limitations in complex, multi-step or multi-signal scenarios; our proposed JSON representation effectively alleviates context-length and parsing bottlenecks, facilitating flexible extension to diverse question types and waveform sources.

0 citationsRead paper

CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems

Jun 24, 2026

This work addresses the challenges of uncontrolled worst-case processor latency and highly variable task execution times in mixed-criticality systems by introducing, for the first time, three real-time microarchitectural enhancements to the open-source CVA6 (RV64GC) processor. These include a TLB with partition locking support, a dynamically reconfigurable scratchpad mode for the L1 cache, and an enhanced interrupt controller featuring hardware-assisted context stacking. Together, these mechanisms ensure deterministic memory access and substantially reduce interrupt response latency. Experimental results demonstrate that with these real-time features enabled, interrupt latency is reduced to 12 cycles—tenfold lower than that of the baseline CVA6—achieving timing predictability comparable to Arm Cortex-M class processors.

0 citationsRead paper

Exploring Fast Fourier Transforms on the Tenstorrent Wormhole

Jun 18, 2025

RISC-V’s adoption in high-performance computing (HPC) remains limited due to a lack of optimized domain-specific workloads. Method: This paper presents the first implementation and deep optimization of 2D Fast Fourier Transform (FFT) on the Tenstorrent Wormhole n300 PCIe accelerator—built upon the RISC-V-based Tensix architecture—leveraging its decoupled compute and data movement hardware to address memory bandwidth bottlenecks via customized optimizations, including memory access reordering and tiling. Numerical accuracy is strictly preserved. Contribution/Results: Experiments show that Wormhole n300 achieves ~8× lower power consumption and 2.8× lower energy consumption than a 24-core Intel Xeon Platinum CPU for 2D FFT. This work demonstrates the practical viability of RISC-V-based accelerators in energy-constrained HPC scenarios and establishes a reusable algorithm-architecture co-design methodology for open instruction set architectures in scientific computing.

0 citationsRead paper