About the job
Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads. Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms. This role is ideal for an architect/micro-architect who enjoys working across hardware and software boundaries, defining next-generation compute architectures, and shaping how CPUs and HPC/AI workloads work together.
Responsibilities
Drive the architecture and micro-architecture of compute execution units and subsystems for HPC and AI inference/training workloads
Translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA)
Work closely with architects, software teams, silicon designers, and external IP partners to enable future HPC/AI computing platforms
Define architectural specifications and lead cross-functional teams from concept through silicon implementation
Design CPU compute that efficiently accelerates modern HPC/AI workloads through optimized matrix floating-point execution and heterogeneous compute architectures
Qualifications
Minimum
5+ years of experience in CPU design for high-performance computing and AI acceleration
Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads
Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators
Experience defining architectural specifications and leading cross-functional teams from concept through silicon implementation
Experience with RTL development with cutting edge AI frontier models
Preferred
No preferred qualifications listed.