About the job
Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline.
Responsibilities
Own physical implementation of IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff
Work closely with RTL owners to close critical paths and hit power budgets
Build floorplans, power grids, pin placement, and clocking strategies
Deliver IP integration collateral including LEF/DEF, timing and power models, GDS, and signoff reports
Port the same block across nodes, foundries, and PPA targets
Qualifications
Minimum
BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout
Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl)
Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)
Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports)
Preferred
No preferred qualifications listed.