Porting and Benchmarking Chapel on Emerging RISC-V Hardware: an HPC Viability Study

2026-08-14

AI Summary

This study addresses the need to evaluate RISC-V’s suitability for high-performance computing (HPC) by presenting the first systematic port of the Chapel programming language to this platform. Leveraging standard HPC benchmark suites, we conduct a comprehensive cross-platform performance comparison that successfully validates Chapel’s adaptability on RISC-V while identifying critical performance anomalies and bottlenecks inherent in cross-architecture migration. The results demonstrate that RISC-V possesses the technical potential to support future HPC workloads effectively. Consequently, this work provides empirical evidence and methodological guidance for integrating emerging instruction set architectures into the broader HPC ecosystem, establishing a foundational baseline for subsequent research and development in this domain.

Abstract

The Chapel programming language recently added support for the RISC-V architecture. Here we discuss what changes were needed for Chapel to work on RISC-V as well as lessons learned from the porting process. We use some of Chapel's extensive benchmark suite to gain further insight into the suitability of the RISC-V architecture for future HPC use. We compare performance on SiFive P550 and Unmatched boards and a Sophon SG2042 with a variety of other recent HPC CPU platforms. Various portability and performance anomalies arose on different architectures and will be discussed. While the RISC-V machines represent smaller preliminary offerings and not HPC-class hardware, these results still provide hope that RISC-V hardware can become viable for HPC in the near future.

Problem

• RISC-V
• High Performance Computing
• Chapel
• Benchmarking
• Portability

Innovation

• Chapel
• RISC-V
• HPC Benchmarking
• Portability
• Performance Analysis