Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs

2026-02-23

AI Summary

This work addresses the high latency and scarce interposer resource consumption caused by super long lines (SLLs) in multi-die FPGAs, which often become critical-path bottlenecks. It presents the first logic resynthesis approach that explicitly leverages die-partitioning information during logic synthesis, proposing an interconnect-aware, LUT-level transformation that simplifies local circuit structures to reduce SLL usage. Integrated into a complete FPGA CAD flow encompassing packing and placement, the method achieves up to 24.8% and 27.38% SLL reduction on EPFL benchmarks for 2-die and 3-die configurations, respectively. On MCNC benchmarks, it yields an average 1.65% SLL reduction without degrading placement quality, and significantly lowers inter-die connectivity in Koios designs, thereby enhancing physical design flexibility.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Multi-die FPGAs enable device scaling beyond reticle limits but introduce severe interconnect overhead across die boundaries. Inter-die connections, commonly referred to as super-long lines (SLLs), incur high delay and consume scarce interposer interconnect resources, often dominating critical paths and complicating physical design. To address this, this work proposes an interconnect-aware logic resynthesis method that restructures the LUT-level netlist to reduce the number of SLLs. The resynthesis engine uses die partitioning information to apply logic resubstitutions, which simplifies local circuit structures and eliminates SLLs. By reducing the number of SLLs early in the design flow, prior to physical implementation, the proposed method shortens critical paths, alleviates pressure on scarce interposer interconnect resources, and improves overall physical design flexibility. We further build a tool flow for multi-die FPGAs by integrating the proposed resynthesis method with packing and placement. Experimental results on the EPFL benchmarks show that, compared with a state-of-the-art framework, the proposed method reduces the number of SLLs by up to 24.8% for a 2-die FPGA and up to 27.38% for a 3-die FPGA. On MCNC benchmarks, our tool flow achieves an average SLL reduction of 1.65% while preserving placement quality. On Koios benchmarks, where fewer removable SLLs exist, several designs still exhibit considerable inter-die edge reductions. Overall, the results confirm that reducing inter-die connections at the logic level is an effective approach for multi-die FPGAs.

Problem

• multi-die FPGAs
• interconnect overhead
• super-long lines
• interposer resources
• critical paths

Innovation

• interconnect-aware
• logic resynthesis
• multi-die FPGA
• super-long lines
• logic resubstitution