About the job
We need an engineer to own the end-to-end silicon diagnostic pipeline. You won’t just be looking at reports; you will be building the engines that generate them. In this role, you will ingest massive volumes of scan failure data and process parameters, using AI-driven methodologies to find the 'needle in the haystack' that is hindering our yield. Your goal is simple but ambitious: Use AI/ML to transform millions of data points into actionable insights that drive aggressive yield ramps and shorten time-to-market.
Responsibilities
AI-Driven Debug: Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures.
Predictive Yield Modeling: Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line.
Holistic Yield Analysis: Look beyond the bitcell. You’ll analyze the interplay between design marginalities, voltage scaling, and manufacturing variations.
Tool Orchestration: Evaluate and implement cutting-edge AI-based EDA tools for root-cause analysis and systematic defect identification.
Cross-Functional Leadership: Act as the 'translator' between the Fab, Design, and Test teams, using data to prove where the silicon is diverging from the simulation.
Qualifications
Minimum
Bachelor's degree plus 8+ years of related experience OR Master's degree plus 6+ years of related experience
3+ years in Silicon Debug, DFT, or Yield Engineering.
Knowledge of Deep Sub-micron (FinFET) effects, including IR drop, crosstalk, and process variation
Experience with Pattern Recognition, Clustering (for defect binning), and Regression models.
Expertise in Python, SQL, and big data environments (Spark, Snowflake, etc.).
Familiarity with industry-standard yield management systems (e.g., PDF Solutions, Synopsys YieldExplorer, or Cadence Clarity).
Preferred
No preferred qualifications listed.