About the job
This role exists to redefine how AI hardware is built by inventing the next wave of hardware development methodology. You will pioneer AI-driven and sophisticated automation techniques that transform how sophisticated ASICs are conceived, explored, and brought to closure. Working shoulder-to-shoulder with an outstanding ASIC development team, you will invent novel architectures and end-to-end workflows that transcend traditional infrastructure, unlocking new levels of capability across logic design, verification, and physical design.
Responsibilities
Take a comprehensive view of the ASIC development lifecycle, identifying cross-stage bottlenecks and opportunities where automation and AI can improve predictability, convergence, and turnaround time.
Identify, curate, and leverage real-time data to enable effective AI models and analytics, working with infrastructure teams to ensure scalable and secure data pipelines.
Establish quantitative metrics to measure efficiency, quality, and cycle-time improvements; use data-driven insights to guide methodology decisions and prioritize investments.
Serve as a technical catalyst within both the team and the wider company by sharing best practices, publishing internal guidelines, and mentoring engineers on emerging AI-enabled development techniques.
Track advances in AI, EDA, and hardware design research, evaluating their applicability and guiding strategic bets that align with long-term product and technology roadmaps.
Qualifications
Minimum
Bachelor's or Master's degree in Computer Science, Computer Engineering, or Electrical Engineering (or equivalent experience).
5+ years of proven industry experience.
A proven track record developing groundbreaking ASIC design frameworks and flows.
High-level programming skills including experience with Python, PERL, Make, and shell scripting.
Experience with AI frameworks including knowledge of agentic flow development.
Standout colleague with excellent verbal and written communication skills.
Preferred
First-hand experience with RTL, functional verification, formal verification, or physical design would be an asset.