runtime integration and os/hardware interface design

Software developers face significant challenges integrating custom hardware—such as AI accelerators—into applications, primarily due to high hardware design expertise requirements and a fundamental abstraction mismatch between software and hardware layers. Method: This paper introduces an end-to-end chip auto-generation methodology tailored for software developers. It accepts high-level object-oriented specifications as input and establishes a one-to-one mapping between software objects and physical chip regions to ensure abstraction consistency. We propose the novel “software–chip structural alignment” paradigm, coupled with object-aligned floorplanning, vertically integrated IP modular construction, and formal verification of hardware interactions via a sequence-based type system. Contribution/Results: The approach enables novice developers to produce synthesizable chip designs while guaranteeing semantic consistency between software behavior and hardware implementation, as well as correctness of hardware communication. It substantially lowers the domain-specific knowledge barrier for hardware design without compromising functional fidelity or correctness guarantees.

To address the lack of systematic continuous verification and secure release mechanisms in open-source hardware design, this paper pioneers the systematic adaptation of software CI/CD paradigms to the hardware domain, proposing a general-purpose framework for automatic hardware specification mining and continuous deployment. Methodologically, it integrates HDL static analysis, machine learning–driven specification inference, formal verification, and cloud-native automated pipelines, implemented in the prototype system Myrtha. Key contributions include: (1) the first CI/CD architecture supporting continuous hardware specification generation, verification, and release; (2) a scalable, automated specification mining mechanism that overcomes traditional manual modeling bottlenecks; and (3) substantial improvements in quality assurance, experimental reproducibility, and cross-team collaboration efficiency for open-source hardware development.

This work addresses the challenge of short embedded-system lifecycles and inflexible driver updates in industrial automation, hindering timely compliance with evolving regulations and market demands. To this end, we propose Wasm-IO—a novel framework that pioneers the adaptation of WebAssembly (Wasm) to safety-isolated peripheral I/O execution. Wasm-IO introduces a first-of-its-kind Wasm-based interrupt priority extension model enabling deterministic, time-isolated interrupt handling, coupled with platform-agnostic inlined driver support and synchronous I/O abstractions to enable standards-compliant driver hot-swapping. Leveraging lightweight containerization, interrupt virtualization, and real-time scheduling, it significantly reduces I/O latency and runtime overhead. Experimental evaluation demonstrates cross-platform portability, strong spatial and temporal isolation, and practical feasibility on real industrial hardware. Wasm-IO establishes a secure, flexible, and sustainably evolvable paradigm for driver execution in industrial embedded systems.

Traditional operating systems suffer from poor scalability on many-core processors and low parallel efficiency due to their inability to perceive application semantics. To address this, we propose NetworkedOS—a novel application-aware, networked OS architecture. Our approach leverages compile-time dynamic instruction dependency analysis to construct a multi-layer network model that explicitly captures runtime dependencies among applications, the kernel, and hardware. We further design an overlapping graph partitioning algorithm to jointly optimize parallel execution and inter-core communication overhead, and implement a runtime process affinity mapping scheduler. Crucially, NetworkedOS breaks the conventional “black-box” OS assumption regarding application semantics for the first time. Experimental evaluation shows that NetworkedOS achieves a 7.11× speedup over Linux on a 128-core system and a 2.01× improvement over Barrelfish on a 64-core system, significantly enhancing scalability and resource utilization under large-scale parallel workloads.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

Identifying critical safety constraints from the vast number of Hardware Abstraction Layer (HAL) interfaces in embedded systems remains challenging, hindering effective fault prevention. Method: This paper proposes a fault-prevention-oriented requirement prioritization approach. Its core innovation is the formal definition of “indisputable relevance,” transforming hardware access constraint identification into a verifiable formal verification problem. The method models HAL interfaces, semantically analyzes real-world failure reports, and leverages model checkers (e.g., CBMC) to automatically generate mathematical proofs—thereby extracting and verifying constraints strongly correlated with system failures or hardware damage. Results: Evaluated on three industrial-grade failure cases involving the SPI bus spidev HAL, the approach successfully identified and formally verified critical requirements. Experimental results demonstrate its feasibility and effectiveness, establishing a novel, verifiable, and traceable paradigm for requirements engineering in high-reliability embedded systems.

Misuse of Hardware Abstraction Layer (HAL) interfaces in embedded systems frequently leads to runtime failures or even hardware damage; conventional software model checking suffers from unpredictable verification outcomes, hindering stable industrial adoption. Method: This paper proposes a continuous verification methodology tailored to HAL interface specifications, grounded in skeleton-based development with iterative functional extension and round-wise model checking. It introduces the first approach enabling cross-iteration reuse of abstract information without formal stepwise correspondence, thereby enhancing verification predictability and stability. The method integrates automated program abstraction inference with lightweight model checking. Results: Evaluated on real-world embedded applications, it successfully passes HAL specification verification across all development iterations and the final implementation, achieving 100% verification success rate—effectively overcoming the verification uncertainty bottleneck in industrial practice.

This study addresses the limitations of software-defined vehicles (SDVs) stemming from tight hardware-software coupling, which hinders modularity, interoperability, real-time performance, and over-the-air (OTA) update capabilities. The work presents the first systematic evaluation of hardware abstraction layer (HAL) mechanisms across automotive and non-automotive domains—including smartphones and industrial automation—and establishes a standardized assessment framework tailored to SDV requirements. Comparative analysis reveals that hypervisor-based HALs excel in security, OTA support, and hardware efficiency, whereas middleware-based HALs offer superior portability and modularity. Building on these insights, the paper proposes a hybrid HAL architecture that synergistically combines the strengths of both approaches, delivering a scalable, lifecycle-aware hardware abstraction solution for SDVs that ensures secure isolation while providing standardized interfaces.

This work addresses the excessive CPU overhead incurred by frequent memory copies in existing inter-process communication (IPC) runtimes during large-scale data exchange for multimodal and AI services, as well as the absence of a unified hardware-software co-designed offload mechanism. The paper proposes the first unified IPC runtime that elevates memory operation offloading to a general-purpose system capability. By integrating asynchronous pipelining, selective cache injection, and a hybrid coordination mechanism, it jointly manages synchronization, cache visibility, and concurrency in shared-memory communication, enabling flexible trade-offs among throughput, latency, and CPU efficiency. Experimental results on real-world workloads demonstrate up to a 22% reduction in instruction count, a 2.1× improvement in throughput, and as much as a 72% decrease in latency.

This work addresses the limitations of traditional application-specific hardware accelerators, which suffer from large area overhead and low utilization, as well as the inability of existing reconfigurable processors to support microcode-level dynamic control flow—such as loops, conditional branches, and exception handling—hindering their efficiency on compute-intensive tasks with complex control logic. To overcome these challenges, this paper introduces, for the first time, a complete dynamic control flow execution mechanism at the microcode level of a runtime-reconfigurable processor. This enables flexible switching of accelerator configurations during execution and facilitates efficient collaboration between general-purpose cores and configurable accelerators. The proposed approach significantly enhances system flexibility and applicability, achieving substantial speedups over conventional general-purpose processors in diverse domains including object detection, ocean simulation, artificial intelligence, and security.