partitioning and interface definition (hardware/software co-partitioning)

To address the lack of systematic continuous verification and secure release mechanisms in open-source hardware design, this paper pioneers the systematic adaptation of software CI/CD paradigms to the hardware domain, proposing a general-purpose framework for automatic hardware specification mining and continuous deployment. Methodologically, it integrates HDL static analysis, machine learning–driven specification inference, formal verification, and cloud-native automated pipelines, implemented in the prototype system Myrtha. Key contributions include: (1) the first CI/CD architecture supporting continuous hardware specification generation, verification, and release; (2) a scalable, automated specification mining mechanism that overcomes traditional manual modeling bottlenecks; and (3) substantial improvements in quality assurance, experimental reproducibility, and cross-team collaboration efficiency for open-source hardware development.

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

This work addresses the limitations of the Category-Partition (CP) testing method, which is often hindered by tedious manual execution and error-prone processes due to a lack of automation and visualization support. To overcome these challenges, the authors design and implement a CP testing tool featuring an integrated graphical user interface that fully automates the entire workflow—from defining parameters, environment variables, categories, and options (including constraints) to constructing test frames and generating test cases. The tool introduces type-aware option specifications (supporting Boolean, integer, real, and string types), a robust constraint-handling mechanism, and multiple combinatorial generation strategies, significantly enhancing both expressiveness and usability. Empirical validation through nine case studies demonstrates that the tool efficiently produces valid CP-compliant test cases, effectively supporting systematic test design.

Identifying critical safety constraints from the vast number of Hardware Abstraction Layer (HAL) interfaces in embedded systems remains challenging, hindering effective fault prevention. Method: This paper proposes a fault-prevention-oriented requirement prioritization approach. Its core innovation is the formal definition of “indisputable relevance,” transforming hardware access constraint identification into a verifiable formal verification problem. The method models HAL interfaces, semantically analyzes real-world failure reports, and leverages model checkers (e.g., CBMC) to automatically generate mathematical proofs—thereby extracting and verifying constraints strongly correlated with system failures or hardware damage. Results: Evaluated on three industrial-grade failure cases involving the SPI bus spidev HAL, the approach successfully identified and formally verified critical requirements. Experimental results demonstrate its feasibility and effectiveness, establishing a novel, verifiable, and traceable paradigm for requirements engineering in high-reliability embedded systems.

Software developers face significant challenges integrating custom hardware—such as AI accelerators—into applications, primarily due to high hardware design expertise requirements and a fundamental abstraction mismatch between software and hardware layers. Method: This paper introduces an end-to-end chip auto-generation methodology tailored for software developers. It accepts high-level object-oriented specifications as input and establishes a one-to-one mapping between software objects and physical chip regions to ensure abstraction consistency. We propose the novel “software–chip structural alignment” paradigm, coupled with object-aligned floorplanning, vertically integrated IP modular construction, and formal verification of hardware interactions via a sequence-based type system. Contribution/Results: The approach enables novice developers to produce synthesizable chip designs while guaranteeing semantic consistency between software behavior and hardware implementation, as well as correctness of hardware communication. It substantially lowers the domain-specific knowledge barrier for hardware design without compromising functional fidelity or correctness guarantees.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This study addresses the challenge of quantifying the complexity and cost induced by external requirement changes when detailed knowledge of a system’s internal logic is unavailable. To this end, the authors propose a black-box assessment method based on a directed graph of component coupling. By analyzing component interfaces and integrating multi-view modeling—graphical, algebraic, and tabular—the approach uniquely links interface characteristics to cost factors, enabling computable bounded estimates of change-induced complexity and associated costs. The method was validated through a large-scale integration case in a retail banking platform, demonstrating its effectiveness and providing architects and operations teams with actionable, quantitative insights for system design and maintenance.

This work proposes a novel software construction paradigm that fundamentally departs from the core assumptions of object-oriented programming. By decoupling problem-domain entities from functional modules, the approach enables independent organization and reuse of functionality, thereby addressing the fragmentation of features and entanglement of responsibilities commonly induced by binding system behavior to individual domain objects. The proposed paradigm adopts a non-object-oriented modular design that substantially mitigates architectural coupling stemming from rigid object boundaries. As a result, it offers a clearer, more flexible, and maintainable pathway for modeling complex systems, overcoming key limitations inherent in traditional object-oriented approaches.

This work addresses the persistent challenge of inconsistent development and execution environments faced by researchers operating across heterogeneous computing platforms—ranging from laptops and workstations to supercomputers and cloud infrastructures. To overcome this, the authors propose a modular and portable software ecosystem featuring a unified command-line interface that enables seamless orchestration and execution of scientific workflows. The system ensures cross-platform consistency, reproducibility, and scalability, thereby streamlining computational research across diverse hardware configurations. Its practical efficacy has been demonstrated through successful integration into the plan4res project under the European Union’s Horizon 2020 initiative, where it effectively supported complex, large-scale scientific workflows in varied computing environments.

Hardware behavior-driven development (BDD) struggles to scale in complex systems due to its reliance on manual extraction of behavioral scenarios from natural-language specifications. To address this, we propose the first systematic integration of large language models (LLMs) into the hardware BDD workflow, introducing an end-to-end framework comprising *specification understanding*, *scenario generation*, and *formal mapping*. This framework automates the translation of textual specifications into executable UVM tests. Leveraging fine-tuned Llama and Qwen models—enhanced by prompt engineering and formal specification transformation techniques—our approach achieves 87% scenario generation accuracy across multiple RISC-V submodules. It reduces manual test development time by 65% on average and enables bidirectional, traceable verification between specifications and tests. By bridging the methodological gap between software BDD and hardware verification, our work establishes a foundation for scalable, specification-centric hardware validation.