hardware prototyping and fpga implementation

This work proposes a personalized prototyping platform for circuit development to address the limitations of traditional tutorial-based approaches, which rely on rigid, fixed-step instructions that fail to accommodate makers’ individualized building and debugging practices. Central to the platform is a circuit-aware enhanced breadboard integrated with hardware-in-the-loop reconfiguration, context-aware guidance algorithms, and in-situ interactive testing techniques. This integration enables, for the first time, nonlinear, real-time, hardware-context-driven guidance and circuit validation. A user study (N=12) demonstrates that the system effectively aligns with users’ unique construction and troubleshooting behaviors, significantly improving both prototyping efficiency and user experience.

To address low efficiency, insufficient coverage, and poor RTL bug detection in FSM-based chip functional verification, this paper proposes an EDA-feedback-driven, closed-loop LLM testbench generation method. Initial testbenches are generated using GPT-3.5 or GPT-4; then, real-time signal-level feedback—including code and state coverage metrics and error diagnostics—from commercial EDA tools (e.g., Synopsys VCS) is integrated into the prompt engineering process, enabling iterative refinement. This work pioneers deep integration of EDA tool feedback into the LLM generation pipeline, supporting coverage-guided automated test generation and concurrent RTL-level bug detection. Evaluated on multiple industrial-grade FSM designs, the method improves code and state coverage by 20–35% over baseline approaches and successfully identifies timing and control-logic bugs missed by manual verification. The approach significantly enhances both verification efficiency and reliability.

This work addresses the limited generalization capability of large language models (LLMs) across hardware description languages, particularly due to the absence of a systematic evaluation framework for VHDL. We propose the first unified framework for LLM-based VHDL generation and evaluation, introducing an automated, verifiable Verilog-to-VHDL benchmark conversion pipeline. The resulting VHDLBench dataset comprises over 200 VHDL modules, each accompanied by complete testbenches. Integrating automated data synthesis, the VUnit/GHDL verification toolchain, and multi-model comparative analysis, our framework enables the first comprehensive assessment of LLM-generated VHDL code in terms of compilability, executability, and functional correctness. This study reveals critical challenges posed by VHDL-specific semantics and structural constructs, laying the groundwork for multilingual hardware design automation.

Hardware description language (HDL) understanding—particularly for VHDL in high-performance microprocessor design—lacks effective AI support. Method: This paper proposes a large language model (LLM) customization framework specifically for HDLs. Its core innovations include: (1) a novel VHDL-specific Extended Pre-Training (EPT) paradigm to enhance modeling of hardware semantics such as sequential logic and parallel constructs; (2) an LLM-as-a-judge automated evaluation framework achieving high agreement with human experts (Spearman’s ρ = 0.92); and (3) a domain-adapted benchmark suite and expert-aligned evaluation protocol. Results: Experiments show EPT improves expert-assessed accuracy from a baseline of 43% to 69%; instruction fine-tuning further raises it to 71%, with projections exceeding 85% on a newly initialized base model—significantly bridging the technical gap in intelligent VHDL comprehension.

The hardware design domain suffers from a scarcity of high-quality instruction-code pairs, reproducible benchmarks, and robust functional correctness verification mechanisms for LLM-assisted RTL design. Method: This paper introduces the first open-source dataset and benchmarking framework tailored for LLM-powered RTL design. It proposes RTLLM 2.0 (for RTL code generation) and AssertEval (for assertion generation) as dual-task benchmarks, and develops a novel RTL-simulation-based data quality filtering method to curate a 7K-sample dataset of high-confidence, functionally verified examples. Contribution/Results: Through systematic instruction-code pair construction, rigorous data cleaning, targeted model fine-tuning, and comprehensive evaluation, the framework significantly improves functional correctness in LLM-generated RTL. Experiments demonstrate that synergistic optimization of data scale, quality, and training strategy systematically enhances model performance—establishing a reproducible, verifiable infrastructure to advance LLMs in hardware design.

This work addresses the lack of systematic and highly reliable pre-silicon verification methodologies for high-performance RISC-V computing chips by proposing and implementing an end-to-end pre-silicon verification closed-loop framework. The framework uniquely integrates industrial-grade UVM functional verification, FPGA-based system-level hardware-software co-verification, and CI/CD automation pipelines, enabling continuous, efficient, and scalable verification on large-scale CPU/FPGA infrastructures. The resulting high-robustness verification infrastructure has already supported strategic European initiatives such as EPI and DARE, significantly enhancing the reliability of RISC-V chip designs and the efficiency of software integration throughout the development lifecycle.

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

Reproducing hardware architectures from academic papers remains challenging due to missing source code and the inherent complexity of hardware description languages (HDLs). To address this, we propose a neuro-symbolic graph framework that enables end-to-end generation of synthesizable Verilog RTL and corresponding verification environments directly from unstructured architectural text. Our approach formalizes architectural blueprints as graphs and encodes functional specifications via symbolic rules, jointly generating RTL modules and testbenches while integrating synthesis, timing analysis, and PPA (power-performance-area) evaluation. We introduce ArchSynthBench—the first architecture-to-hardware synthesis benchmark—comprising 50 system-level circuits and 600 modules, and decouple design and verification to enhance correctness and debuggability. Experiments show that all generated RTL meets timing constraints, matches original performance metrics, and achieves higher code completion and architectural understanding accuracy than state-of-the-art baselines (e.g., VerilogCoder).

This work addresses the ongoing challenge of automatically translating natural language specifications into editable printed circuit board (PCB) schematics for embedded and IoT development. It presents the first end-to-end approach that leverages tool-augmented large language model reasoning, integrating component library retrieval, datasheet knowledge extraction, execution validation, and structural-semantic verification to generate KiCad-compliant schematics. The system supports iterative refinement through an interactive web interface and achieves a pass@1 rate of 0.90 and a pass@5 rate of 1.00 across 20 embedded schematic generation tasks. This method efficiently produces high-quality initial drafts suitable for early-stage prototype review, substantially advancing the state of hardware design automation.

This work addresses the challenge that large language models (LLMs) often generate erroneous RTL code due to ambiguous or misinterpreted specifications, with such errors typically surfacing only during simulation and proving difficult to trace. To mitigate this, the paper proposes VeriRefine, a novel approach that first refines informal specifications into explicit Abstract Signal Transition Functions (ASTFs)—serving as a verifiable prelude to RTL generation. The method incorporates a five-layer auditing mechanism to validate design intent across dimensions including completeness, consistency, and FSM integrity, and enables targeted debugging by tracing simulation failures back to either specification misunderstandings or coding errors. Evaluated on RTLLM v2.0 and VerilogEval-Human v2, VeriRefine achieves functional correctness rates of 94.0% and 98.1%, respectively, substantially enhancing the reliability and synthesizability of LLM-generated RTL.