Nils Wistoff
Scholar

Nils Wistoff

Google Scholar ID: dh2AR-EAAAAJ
PhD Student, ETH Zurich
processor designsecure computer architecture
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Citations & Impact
All-time
Citations
242
 
H-index
10
 
i10-index
10
 
Publications
20
 
Co-authors
40
list available
Contact
No contact links provided.
Publications
8 items
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
2025
Cited
0
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
2025
Cited
0
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance
2025
Cited
0
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
2025
Cited
0
ArtistIC: An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
2025
Cited
0
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET
2025
Cited
0
A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
IEEE International Conference on Application-Specific Systems, Architectures, and Processors · 2022
Cited
31
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
IEEE transactions on computers · 2022
Cited
13
Resume (English only)
Co-authors
40 total
Luca Benini
Luca Benini
ETH Zürich, Università di Bologna
Frank K. Gürkaynak
Frank K. Gürkaynak
Senior Scientist, ETH Zurich
Gernot Heiser
Gernot Heiser
Professor of Computer Science, University of New South Wales
Davide Rossi
Davide Rossi
Associate Professor, University Of Bologna
Matheus Cavalcante
Matheus Cavalcante
Stanford University
Co-author 6
Co-author 6
Gianmarco Ottavi
Gianmarco Ottavi
University of Bologna
Matteo Perotti
Matteo Perotti
ETH Zürich