Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution

2025-05-30

AI Summary

High-performance open-source RISC-V cores (e.g., C910, CVA6) face deployment bottlenecks in automotive and aerospace applications due to inadequate EDA tool support and non-standardized interfaces—such as C910’s custom AXI extensions and proprietary interrupt/debug protocols. Method: This work conducts the first systematic, silicon-validated comparison of three superscalar out-of-order RISC-V cores—C910, CVA6S+, and CVA6—implemented on the open-source Cheshire SoC platform in 22 nm, employing ISA-compliant modifications, Chisel/HDL hybrid design, standardized AXI/interrupt/debug interface reconstruction, and full-flow EDA implementation. Contribution/Results: CVA6S+ achieves a 34.4% IPC gain with only 6% area overhead, delivering optimal area efficiency. C910 attains a 119.5% IPC improvement (+75% area), yet achieves state-of-the-art GOPS/W energy efficiency—challenging the “high performance implies high power” paradigm. The study provides quantitative, application-aware guidance for RISC-V microarchitecture selection in safety-critical heterogeneous domains.

Technology Category

• Computer Vision: Learning & Optimization for CV
• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including non-standard AXI protocol extensions, interrupts, and debug support. In this work, we present a modified version of the OoO C910 core to achieve full RISC-V standard compliance in its debug, interrupt, and memory interfaces. We also introduce CVA6S+, an enhanced version of the dual-issue, industry-supported open-source CVA6 core. CVA6S+ achieves 34.4% performance improvement over CVA6 core. We conduct a detailed performance, area, power, and energy analysis on the superscalar out-of-order C910, superscalar in-order CVA6S+ and vanilla, single-issue in-order CVA6, all implemented in a 22nm technology and integrated into Cheshire, an open-source modular SoC. We examine the performance and efficiency of different microarchitectures using the same ISA, SoC, and implementation with identical technology, tools, and methodologies. The area and performance rankings of CVA6, CVA6S+, and C910 follow expected trends: compared to the scalar CVA6, CVA6S+ shows an area increase of 6% and an IPC improvement of 34.4%, while C910 exhibits a 75% increase in area and a 119.5% improvement in IPC. However, efficiency analysis reveals that CVA6S+ leads in area efficiency (GOPS/mm2), while the C910 is highly competitive in energy efficiency (GOPS/W). This challenges the common belief that high performance in superscalar and out-of-order cores inherently comes at a significant cost in area and energy efficiency.

Problem

• Assessing energy efficiency of superscalar RISC-V cores
• Achieving full RISC-V standard compliance in interfaces
• Comparing performance and efficiency of different microarchitectures

Innovation

• Modified OoO C910 core for RISC-V compliance
• Enhanced dual-issue CVA6S+ with 34.4% performance boost
• Detailed analysis of superscalar in-order and OoO cores