A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications

2025-02-26

AI Summary

Mixed-criticality edge AI applications in robotics, automotive, and aerospace demand stringent temporal predictability and high reliability under shared hardware resources. Method: We propose a 16 nm heterogeneous SoC featuring (i) a novel hardware–software co-designed configurable IP mechanism enabling deterministic interconnect and memory access, and (ii) a highly reliable multi-core AI accelerator coupled with a dual-core vector cluster, supporting strict spatial and temporal isolation between critical and non-critical workloads. Contribution/Results: The AI accelerator achieves 304.9 GOPS at 1.6 TOPS/W; the vector cluster delivers 121.8 GFLOPS at 1.1 TFLOPS/W. The entire SoC operates within ≤1.2 W power envelope while satisfying rigorous worst-case execution time (WCET) constraints—demonstrating simultaneous breakthroughs in energy efficiency and timing determinism for safety-critical edge AI.

Technology Category

• Machine Learning: Hardware-aware ML
• Philosophy and Ethics of AI: Safety, Robustness & Trustworthiness
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Security and Privacy: Security and privacy of machine learning and AI applications
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs

Abstract

Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges, in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm2.

Problem

• Ensures reliable, time-predictable execution of critical tasks
• Integrates software-configurable hardware IPs for predictable resource access
• Accelerates mixed-precision AI and floating-point workloads efficiently

Innovation

• 16nm heterogeneous SoC design
• software-configurable hardware IPs
• multi-core AI accelerator