Scholar
Michael Rogenmoser
Google Scholar ID: Tik4hScAAAAJ
ETH Zurich
Fault Tolerance
Multicore processors
Reliable SoCs
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Citations & Impact
All-time
Citations
131
H-index
6
i10-index
5
Publications
16
Co-authors
0
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Publications
8 items
Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
2026
Cited
0
Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges
2026
Cited
0
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
2026
Cited
0
Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
2026
Cited
0
A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
2025
Cited
0
relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
2025
Cited
0
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
2025
Cited
0
Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
IEEE Transactions on Nuclear Science · 2024
Cited
1
Resume (English only)
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Co-authors: 0 (list not available)
