From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation

2026-04-10

AI Summary

This work addresses the inefficiency of traditional LLM-based assertion generation methods, which overlook signal criticality in hardware verification. To overcome this limitation, the authors propose AgileAssert, a novel framework that integrates functional critical signal identification with LLM-driven assertion synthesis for the first time. AgileAssert constructs RTL semantic graphs to identify critical signals, employs a hybrid scoring mechanism for signal selection, and introduces structure-aware RTL slicing to provide precise contextual information to the LLM, thereby guiding it to generate targeted, constraint-based assertions. Experimental results demonstrate that AgileAssert reduces assertion count by 66.68% on average across module- and CPU-level designs while improving coverage and cutting input token consumption by 64%. In mutation testing, it achieves higher fault detection rates with 72.74% fewer assertions, significantly enhancing both verification efficiency and precision.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Search and Retrieval-Augmented AI: Agentic search
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-based assertion generation methods typically pursue indiscriminate verification, aiming for maximal coverage without considering signal criticality, whereas industrial practice demands maximizing coverage with minimal verification cost. Consequently, identifying signals that have the greatest impact on design functionality and error propagation-enabling a shift from indiscriminate to targeted verification-remains a key challenge. To address this, we propose AgileAssert, a key signal-driven assertion generation framework that constructs RTL semantic graphs and identifies the top-K critical signals via a hybrid scoring and selection mechanism, followed by structure-aware RTL slicing to provide the LLM with precise targets and contextual information, thereby guiding LLMs to generate tightly constrained targeted assertions for efficient verification. Evaluated on block- and CPU-level designs, with an average 66.68% reduction in assertions, our approach outperforms three existing SOTA methods, and significantly improving coverage metrics while reducing input token consumption by 64%. In mutation testing, when our approach surpasses existing methods in error detection rate, the average number of assertions used decreases by 72.74%.

Problem

• RTL verification
• Assertion-Based Verification
• key signal identification
• targeted verification
• functional coverage

Innovation

• key signal-driven
• targeted assertion generation
• RTL semantic graph
• structure-aware slicing
• LLM-guided verification