AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking

2026-03-26

AI Summary

This work addresses the high sensitivity of Property Directed Reachability (PDR) algorithm performance in hardware model checking to parameter configuration, a challenge exacerbated by the prohibitive cost of manual tuning and the inefficiency of conventional automated methods. To overcome this, the authors propose a novel solver configuration prediction framework that integrates circuit graph structure with static features. For the first time, graph neural networks are combined with expert prior knowledge to enable intelligent prediction of PDR heuristic strategies tailored to specific circuits. By leveraging topological analysis and constraint-driven filtering of invalid configurations, the approach dramatically reduces the search space by 78%. Evaluated on standard benchmarks, it substantially outperforms both default and commonly used configurations, significantly enhancing verification efficiency while uncovering circuit-specific parameter patterns.

Technology Category

• Search and Optimization: Algorithm Configuration
• Constraint Satisfaction and Optimization: Solvers and Tools
• Machine Learning: Probabilistic Circuits and Graphical Models

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

Property Directed Reachability (PDR) is a powerful algorithm for formal verification of hardware and software systems, but its performance is highly sensitive to parameter configurations. Manual parameter tuning is time-consuming and requires domain expertise, while traditional automated parameter tuning frameworks are not well-suited for time-sensitive verification tasks like PDR. This paper presents a circuit-aware solver configuration framework that employs graph learning for intelligent heuristic selection in PDR-based verification. Our approach combines graph representations with static circuit features to predict optimal PDR solving configurations for specific circuits. We incorporate expert prior knowledge through constraint-based parameter filtering to eliminate invalid and inefficient configurations and reduce 78% search space. Our feature extraction pipeline captures structural, functional, and connectivity characteristics of circuit topology and component patterns. Experimental evaluation on a comprehensive benchmark suite demonstrates significant performance improvements compared to default configurations and commonly-used settings. The system successfully identifies circuit-specific parameter patterns and automatically selects the most suitable solving strategies based on circuit characteristics, making it a practical tool for automated formal verification workflows.

Problem

• Property Directed Reachability
• solver configuration
• hardware model checking
• parameter tuning
• formal verification

Innovation

• circuit-aware
• graph learning
• PDR
• solver configuration
• formal verification