EDA-Driven Preprocessing for SAT Solving

2024-03-28

arXiv.org

AI Summary

Existing SAT solvers are optimized for CNF input and thus inefficient for Circuit Satisfiability (CSAT) problems. This paper addresses this limitation by proposing an EDA-driven dual-format preprocessing framework that jointly leverages native circuit structure and CNF representation, overcoming the bottleneck of conventional CNF-only modeling. Methodologically, the framework introduces two key innovations: (1) a reinforcement learning–guided logic synthesis technique that dynamically optimizes circuit structure to enhance solver compatibility; and (2) a cost-customized LUT-mapping strategy enabling efficient, low-overhead translation from circuit to CNF. Evaluated on SAT Competition benchmarks, the framework achieves an average speedup of 52.42%; in logic equivalence checking tasks, it delivers a 96.14% runtime reduction. These results demonstrate substantial improvements in both CSAT solving efficiency and generalization capability across diverse verification scenarios.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability
• Search and Optimization: Mixed Discrete/Continuous Search
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Effective formulation of problems into Conjunctive Normal Form (CNF) is critical in modern Boolean Satisfiability (SAT) solving for optimizing solver performance. Addressing the limitations of existing methods, our Electronic Design Automation (EDA)-driven preprocessing framework introduces a novel methodology for preparing SAT instances, leveraging both circuit and CNF formats for enhanced flexibility and efficiency. Central to our approach is the integration of a new logic synthesis technique, guided by a reinforcement learning agent, and a novel cost-customized LUT mapping strategy, enabling efficient handling of diverse SAT challenges. By transforming the SAT competition benchmarks into circuit instances, our framework demonstrates substantial performance improvements, as evidenced by a 52.42% reduction on average compared to solving directly. Moreover, our framework achieves a remarkable 96.14% runtime reduction on average for a set of logic equivalence checking problems that exhibit inherent circuit structures. These results highlight the effectiveness and versatility of our approach in handling both CNF and circuit instances. The code is available at https://github.com/cure-lab/EDA4SAT.

Problem

• Optimizing CSAT solving for circuit design complexity
• Enhancing SAT solvers with logic synthesis techniques
• Reducing runtime in industrial-scale CSAT benchmarks

Innovation

• Leverages logic synthesis and reinforcement learning
• Cost-customized LUT mapping for efficiency
• Transforms circuits into simplified SAT forms