You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors

2026-08-11

AI Summary

This work addresses the “ADC wall” bottleneck in analog compute-in-memory (ACiM) systems—caused by the high energy consumption and large area of analog-to-digital converters (ADCs), compounded by repeated ADC invocations in bit-slicing execution—by proposing Charge-CIM, a novel architecture. Charge-CIM unifies input conversion, analog MAC computation, weighted shift-and-accumulate, and quantized readout within a single reconfigurable switched-capacitor array based on charge redistribution. By employing a differential readout path that merges paired partial sums directly at the ADC stage, it eliminates both standalone ADC overhead and intermediate conversion steps. Experimental results across multiple DNN models demonstrate that, compared to the state-of-the-art charge-domain CIM accelerators, Charge-CIM reduces ADC energy by 91.7%, improves energy efficiency by 2.7×, and achieves 2.0× higher throughput.

Abstract

Analog Computing-in-Memory (ACiM) accelerates deep neural networks by keeping weights inside memory arrays and executing dot products in the analog domain. However, modern ACiM accelerators are often limited by the "ADC wall": analog-to-digital converters consume a large fraction of energy and area, while bit-sliced execution repeatedly invokes these converters. Existing designs reduce this cost with low-resolution readout or time multiplexing, but they either lose output fidelity or introduce serialization overhead. Charge-CIM addresses this bottleneck by using switched-capacitor charge redistribution as a unified computing and conversion substrate. The same capacitor fabric performs input conversion, analog MAC, weighted shift-and-add, and readout quantization, reducing both standalone converter overhead and intermediate ADC invocations. A differential readout path further combines paired partial sums during ADC quantization, providing a highly compact and energy-efficient solution for array integration. With dataflow architecture support, we evaluated Charge-CIM on a suite of DNN benchmarks, from CNNs to Transformer models, and experimental results show that Charge-CIM reduces ADC energy by 91.7% under our evaluation setup and improves energy efficiency by 2.7x and throughput by 2.0x compared to the state-of-the-art charge-domain CIM accelerator.

Problem

• Analog Computing-in-Memory
• ADC wall
• energy efficiency
• deep neural networks
• analog-to-digital conversion

Innovation

• Analog Computing-in-Memory
• Switched Capacitors
• Charge Redistribution
• ADC Wall
• Differential Readout