ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression

2026-08-09

AI Summary

This work addresses the excessive instruction footprint caused by node-by-node code generation in RTL simulation, which induces CPU frontend bottlenecks and pipeline stalls. The authors propose a node compression technique that enables multiple nodes to share a single instruction sequence through module-aware identification of isomorphic subgraphs, alignment-aware dense packing, and a unified bit-level parallel execution mechanism. By integrating structural isomorphism analysis, dataflow dependency grouping, and greedy merging, the method significantly enhances simulation efficiency while preserving code compactness. Experimental results demonstrate 1.6× and 2.7× simulation speedups on general-purpose CPUs and AI accelerator designs, respectively, substantially outperforming state-of-the-art simulators.

Abstract

RTL simulation is indispensable in chip design. High-performance simulators typically lower each node in the RTL graph into an instruction sequence. Although this per-node lowering enables aggressive compiler optimizations, it dramatically increases the code footprint, severely exceeding instruction cache capacity and causing front-end bottlenecks. Our profiling reveals that over 50% of pipeline stalls are caused by the CPU front-end, becoming a key performance bottleneck in state-of-the-art RTL simulators. However, reaping the optimization benefits of fully unrolling the RTL graph while simultaneously reducing the code footprint to mitigate front-end bottlenecks remains highly challenging. In this paper, we propose ARMOR, an efficient RTL simulator designed to alleviate the front-end bottleneck through node compression. The key idea is to exploit the data parallelism exposed by the unrolling RTL graph and the insufficient bit-space utilization revealed by per-node lowering, leveraging bit-level data parallelism to compress multiple nodes simultaneously, so that a single instruction sequence can serve multiple nodes instead of one per node. To achieve profitable node compression, we first propose a module-aware isomorphic subgraph identification method that leverages structural isomorphism across module instances to systematically identify compression opportunities at the subgraph level. We then propose an alignment-aware dense packing strategy that groups nodes into packs according to dataflow dependencies while preserving data reuse, complemented by greedy merging strategies to enhance bit-space utilization. Finally, we implement a unified bit-level parallelism scheme to support bit-level parallel execution of compressed nodes. Experimental results show that ARMOR achieves 1.6x speedup on CPU designs and 2.7x speedup on AI accelerators compared to state-of-the-art simulators.

Problem

• RTL simulation
• front-end bottleneck
• instruction cache
• code footprint
• pipeline stalls

Innovation

• node compression
• bit-level parallelism
• RTL simulation
• front-end bottleneck
• isomorphic subgraph