A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS

2024-11-18

ICCD

AI Summary

To address low design efficiency and coarse-grained energy-efficiency control in heterogeneous SoC development, this paper proposes a rapid design-space exploration and runtime co-optimization methodology for large-scale FPGA-based many-core architectures. Our approach introduces, for the first time, a multi-accelerator replica instantiation mechanism within a single Network-on-Chip (NoC) node, coupled with fine-grained frequency-domain partitioning and independent dynamic frequency scaling (DFS) control, integrated with a lightweight runtime monitoring infrastructure. Built upon the ESP framework, it synergistically combines prototype-driven design, NoC topology modeling, and real-time performance and interconnect traffic awareness. Evaluated on a 4×4 tile architecture, the method enables three-dimensional co-optimization of accelerator replication, frequency island configuration, and tile placement. Experimental results demonstrate a 3.2× speedup in design-space exploration and a 41% improvement in runtime energy efficiency.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of de-signing such architectures. The open-source Vespa framework for designing large, FPGA-based, multi-core heterogeneous system-on-chips enables a faster and more flexible design space exploration of such architectures and their run-time optimization. Vespa, built on ESP, introduces the capabilities to instantiate multiple replicas of the same accelerator in a single network-on-chip node and to partition the system-on-chips into frequency islands with independent dynamic frequency scaling actuators, as well as a dedicated run-time monitoring infrastructure. Experiments on 4-by-4 tile-based system-on-chips demonstrate the possibility of effectively exploring a multitude of solutions that differ in the replication of accelerators, the clock frequencies of the frequency islands, and the tiles' placement, as well as monitoring a variety of statistics related to the traffic on the interconnect and the accelerators' performance at run time.

Problem

• System-on-Chip (SoC)
• Design Efficiency
• Scalability

Innovation

• Vespa Framework
• System-on-Chip (SoC) Optimization
• Multi-Accelerator Integration