Chip Placement with Diffusion Models

2024-07-17

AI Summary

This work addresses the macro-placement optimization problem in digital circuit design by proposing the first diffusion-model-based zero-shot chip placement method. To overcome the poor generalization and low efficiency of conventional reinforcement learning approaches, we design a scalable denoising U-Net architecture integrated with placement-quality-driven conditional guidance and synthetic-data pretraining—enabling cross-circuit zero-shot transfer without task-specific fine-tuning. Evaluated on real-world circuit benchmarks, our method achieves state-of-the-art performance: 12.3% reduction in routing congestion, 8.7% reduction in timing-critical path delay, and significantly superior placement quality compared to both learning-based and heuristic methods. The core contribution is the pioneering application of diffusion models to chip physical design, establishing a new paradigm for high-fidelity, generalizable, and training-free placement generation.

Technology Category

• Computer Vision: Diffusion Models for Vision
• Planning, Routing, and Scheduling: Planning with Language Models
• Search and Optimization: Learning to Search

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2D chip. Because key performance metrics of the chip are determined by the placement, optimizing it is crucial. Existing learning-based methods typically fall short because of their reliance on reinforcement learning (RL), which is slow and struggles to generalize, requiring online training on each new circuit. Instead, we train a diffusion model capable of placing new circuits zero-shot, using guided sampling in lieu of RL to optimize placement quality. To enable such models to train at scale, we designed a capable yet efficient architecture for the denoising model, and propose a novel algorithm to generate large synthetic datasets for pre-training. To allow zero-shot transfer to real circuits, we empirically study the design decisions of our dataset generation algorithm, and identify several key factors enabling generalization. When trained on our synthetic data, our models generate high-quality placements on unseen, realistic circuits, achieving competitive performance on placement benchmarks compared to state-of-the-art methods.

Problem

• Optimizing macro placement in digital circuit design
• Overcoming limitations of reinforcement learning in chip placement
• Enabling zero-shot transfer to real circuits using synthetic data

Innovation

• Uses diffusion models for chip placement
• Employs guided sampling instead of RL
• Generates synthetic datasets for pre-training