Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA

2026-08-11

AI Summary

This study addresses the challenge posed by next-generation synthetic aperture radar (SAR) missions, where on-board data volumes vastly exceed downlink capacity, necessitating efficient in-orbit processing. The authors propose a joint despeckling and compression (DDC) framework tailored for embedded platforms and demonstrate its end-to-end deployment on a ZCU102 FPGA. By replacing the generalized divisive normalization (GDN) with a discoverable ReLU, adopting a lightweight network architecture, and applying fixed-point quantization, the design effectively balances performance with hardware constraints. Experimental results indicate that residual blocks introduce additional overhead without yielding significant gains. This work presents the first on-board FPGA implementation of joint SAR processing, validating its advantages in energy efficiency and real-time operation, and establishes a reproducible edge computing paradigm for future intelligent SAR on-board processing.

Abstract

Next-generation Synthetic Aperture Radar (SAR) missions will generate data far faster than they can downlink, making onboard data reduction essential for near-real-time Earth observation. Learned Image Compression (LIC) offers better rate-distortion performance than handcrafted codecs used operationally today, and recent work shows that simultaneously despeckling and compressing SAR imagery enables better representation capacity while unlocking higher compression rates. These methods, however, have yet to be confronted with the strict power, compute, and operational constraints of spaceborne systems. In this work, we bridge this gap by deploying a joint SAR Despeckling and Data Compression (DDC) framework on an embedded ZCU102 FPGA-based platform, introducing model adaptations that respect the accelerator's fixed-point arithmetic and limited set of supported operations. We evaluate four model topologies across precision levels and across CPU, GPU, and FPGA platforms, revealing several findings with direct design implications. We find that replacing conventional GDN activation functions with plain ReLU improves quality on SAR, suggesting that design principles established for compression of natural images do not necessarily transfer to SAR imagery. In addition, we demonstrate that residual blocks offer little representational benefit for ten times the compute, and show that the FPGA is the most energy-efficient of the platforms tested. Together, these results set a functioning edge deployment workflow and an evidence-based starting point for onboard SAR compression. The code is available at https://github.com/CedricLeon/SAR_DDC_FPGA.

Problem

• Synthetic Aperture Radar
• onboard compression
• despeckling
• FPGA deployment
• hardware-aware

Innovation

• FPGA deployment
• SAR despeckling
• learned image compression
• hardware-aware optimization
• fixed-point arithmetic