Selected work

Representative Papers

Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA

Aug 11, 2026

This study addresses the challenge posed by next-generation synthetic aperture radar (SAR) missions, where on-board data volumes vastly exceed downlink capacity, necessitating efficient in-orbit processing. The authors propose a joint despeckling and compression (DDC) framework tailored for embedded platforms and demonstrate its end-to-end deployment on a ZCU102 FPGA. By replacing the generalized divisive normalization (GDN) with a discoverable ReLU, adopting a lightweight network architecture, and applying fixed-point quantization, the design effectively balances performance with hardware constraints. Experimental results indicate that residual blocks introduce additional overhead without yielding significant gains. This work presents the first on-board FPGA implementation of joint SAR processing, validating its advantages in energy efficiency and real-time operation, and establishes a reproducible edge computing paradigm for future intelligent SAR on-board processing.

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Conditional Invertible Neural Networks for Data-Driven UAV Control: A 2-D Proof of Concept

Jul 15, 2026

This study addresses the limited generalization of inverse dynamics models and inadequate uncertainty quantification in data-driven control of multirotor unmanned aerial vehicles. To this end, it introduces conditional invertible neural networks (CINNs) into this domain for the first time, leveraging incremental nonlinear dynamic inversion (INDI) as a teacher policy for supervised training. The proposed architecture employs rational quadratic spline coupling layers combined with invertible linear mixing to explicitly learn the probabilistic distribution of control inputs, thereby effectively capturing model uncertainty and revealing the critical influence of data coverage and command bandwidth on control failure. Experimental results on an X8 coaxial multirotor demonstrate an open-loop reproduction R² of 0.944 and a continuous ranked probability score (CRPS) of 0.0915; in closed-loop tests across 15 scenarios, the method achieves a position RMSE of 9.7 m and a tracking success rate of 47%, matching INDI’s performance while successfully identifying two dominant failure modes.

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HORCRUX: A Complete PQC RISC-V eXtension Architecture

Jul 15, 2026

This work addresses the challenge of simultaneously achieving algorithmic agility, high performance, and low overhead for post-quantum cryptography (PQC) in resource-constrained embedded systems. The authors propose a compact RISC-V instruction set extension architecture that, for the first time, unifies support for all NIST-standardized PQC algorithms within a single hardware implementation. Integrated with a lightweight tightly coupled coprocessor, the design enhances both energy and area efficiency while maintaining backward compatibility with standard RISC-V cores. Implemented on a Zynq UltraScale+ FPGA, the architecture achieves speedups of up to 129×, 9×, and 27× for hash-based, lattice-based, and code-based schemes, respectively, with an overhead of less than 21k LUTs and 4.4k FFs. ASIC synthesis results in a 65nm process further confirm its superior energy efficiency.

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On Adversarial Vulnerability of Vision-Language Models through the Lens of Intermediate Spectral Subspaces

Jul 08, 2026

This study investigates the vulnerability mechanisms of vision-language models under adversarial attacks, with a focus on how the spectral structure of intermediate linear transformations influences model robustness. To this end, the authors propose a white-box Spectral Subspace-Guided Attack (SSGRA), which enhances attack efficacy by aligning intermediate representations with the subspace spanned by right singular vectors. This work is the first to reveal the adversarial fragility of vision-language models from the perspective of spectral subspaces, achieving higher attack success rates than existing baselines. Moreover, it offers novel theoretical insights and a principled technical pathway toward understanding and improving the robustness of such models.

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Hardware-Enforced Semantic Coordination for Safety-Critical Real-Time Autonomous Systems

Jul 02, 2026

This work addresses the challenge of achieving bounded, verifiable, and deterministic coordination in safety-critical real-time autonomous systems operating under uncertainty. It proposes a hardware-enforced semantic coordination architecture that, for the first time, directly maps a topic-based communication space Petri net (TB-CSPN) coordination mechanism onto the FPGA hardware layer. By leveraging hardware primitives to construct a native semantic coordination layer, the approach ensures deterministic execution of time synchronization, semantic gating, authorization constraints, and bounded coordination behaviors—without relying on software mediation. The design decouples low-level interaction management from high-level semantic reasoning, thereby preserving software adaptability while guaranteeing hardware-level reliability. This integration yields a highly dependable real-time system architecture with formally verifiable safety assurances, deterministic coordination, and bounded latency.

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Recent publications

Latest Papers

Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA

Aug 11, 2026

This study addresses the challenge posed by next-generation synthetic aperture radar (SAR) missions, where on-board data volumes vastly exceed downlink capacity, necessitating efficient in-orbit processing. The authors propose a joint despeckling and compression (DDC) framework tailored for embedded platforms and demonstrate its end-to-end deployment on a ZCU102 FPGA. By replacing the generalized divisive normalization (GDN) with a discoverable ReLU, adopting a lightweight network architecture, and applying fixed-point quantization, the design effectively balances performance with hardware constraints. Experimental results indicate that residual blocks introduce additional overhead without yielding significant gains. This work presents the first on-board FPGA implementation of joint SAR processing, validating its advantages in energy efficiency and real-time operation, and establishes a reproducible edge computing paradigm for future intelligent SAR on-board processing.

0 citationsRead paper

Conditional Invertible Neural Networks for Data-Driven UAV Control: A 2-D Proof of Concept

Jul 15, 2026

This study addresses the limited generalization of inverse dynamics models and inadequate uncertainty quantification in data-driven control of multirotor unmanned aerial vehicles. To this end, it introduces conditional invertible neural networks (CINNs) into this domain for the first time, leveraging incremental nonlinear dynamic inversion (INDI) as a teacher policy for supervised training. The proposed architecture employs rational quadratic spline coupling layers combined with invertible linear mixing to explicitly learn the probabilistic distribution of control inputs, thereby effectively capturing model uncertainty and revealing the critical influence of data coverage and command bandwidth on control failure. Experimental results on an X8 coaxial multirotor demonstrate an open-loop reproduction R² of 0.944 and a continuous ranked probability score (CRPS) of 0.0915; in closed-loop tests across 15 scenarios, the method achieves a position RMSE of 9.7 m and a tracking success rate of 47%, matching INDI’s performance while successfully identifying two dominant failure modes.

0 citationsRead paper

HORCRUX: A Complete PQC RISC-V eXtension Architecture

Jul 15, 2026

This work addresses the challenge of simultaneously achieving algorithmic agility, high performance, and low overhead for post-quantum cryptography (PQC) in resource-constrained embedded systems. The authors propose a compact RISC-V instruction set extension architecture that, for the first time, unifies support for all NIST-standardized PQC algorithms within a single hardware implementation. Integrated with a lightweight tightly coupled coprocessor, the design enhances both energy and area efficiency while maintaining backward compatibility with standard RISC-V cores. Implemented on a Zynq UltraScale+ FPGA, the architecture achieves speedups of up to 129×, 9×, and 27× for hash-based, lattice-based, and code-based schemes, respectively, with an overhead of less than 21k LUTs and 4.4k FFs. ASIC synthesis results in a 65nm process further confirm its superior energy efficiency.

0 citationsRead paper

On Adversarial Vulnerability of Vision-Language Models through the Lens of Intermediate Spectral Subspaces

Jul 08, 2026

This study investigates the vulnerability mechanisms of vision-language models under adversarial attacks, with a focus on how the spectral structure of intermediate linear transformations influences model robustness. To this end, the authors propose a white-box Spectral Subspace-Guided Attack (SSGRA), which enhances attack efficacy by aligning intermediate representations with the subspace spanned by right singular vectors. This work is the first to reveal the adversarial fragility of vision-language models from the perspective of spectral subspaces, achieving higher attack success rates than existing baselines. Moreover, it offers novel theoretical insights and a principled technical pathway toward understanding and improving the robustness of such models.

0 citationsRead paper

Hardware-Enforced Semantic Coordination for Safety-Critical Real-Time Autonomous Systems

Jul 02, 2026

This work addresses the challenge of achieving bounded, verifiable, and deterministic coordination in safety-critical real-time autonomous systems operating under uncertainty. It proposes a hardware-enforced semantic coordination architecture that, for the first time, directly maps a topic-based communication space Petri net (TB-CSPN) coordination mechanism onto the FPGA hardware layer. By leveraging hardware primitives to construct a native semantic coordination layer, the approach ensures deterministic execution of time synchronization, semantic gating, authorization constraints, and bounded coordination behaviors—without relying on software mediation. The design decouples low-level interaction management from high-level semantic reasoning, thereby preserving software adaptability while guaranteeing hardware-level reliability. This integration yields a highly dependable real-time system architecture with formally verifiable safety assurances, deterministic coordination, and bounded latency.

0 citationsRead paper