CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations

2026-04-07

AI Summary

This work addresses the limitation of large language models (LLMs) in generating SystemVerilog assertions that often fail to cover critical functional behaviors due to insufficient understanding of circuit designs. To overcome this, the authors propose CoverAssert, an iterative framework that, for the first time, integrates a syntax–semantics joint representation—based on abstract syntax trees and semantic feature clustering—with a functional coverage feedback mechanism. This approach maps assertions to natural language specifications and guides the LLM to prioritize generating assertions for uncovered scenarios. Experimental results on four open-source designs demonstrate that integrating AssertLLM with Spec2Assertion yields average improvements of 9.57%, 9.64%, and 15.69% in branch, statement, and toggle coverage, respectively, substantially enhancing verification completeness.

Abstract

LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.

Problem

• LLM
• SystemVerilog assertion
• functional coverage
• IC design
• natural language specification

Innovation

• functional coverage
• iterative LLM
• syntax-semantic representation
• SystemVerilog assertion
• coverage-guided generation