Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation

2026-05-25

AI Summary

This work addresses the limitations of current large language models in generating Verilog code that, while functionally correct, is often unsynthesizable and lacks timing awareness, thus failing to meet practical RTL design requirements. To overcome this, the authors propose a feedback-driven iterative refinement framework that employs a multi-round generate–evaluate–promote mechanism. This framework integrates multidimensional feedback from functional simulation, Yosys synthesis, an ABC-based timing proxy, and GEMM-specific metrics to progressively enhance code quality. Novel strategies—including versioned refinement, cross-session skill evolution, and verification-gated skill updates—enable modular skill retrieval and history-aware decisions for skill creation, improvement, or skipping. Evaluated on VerilogEval and mixed-precision GEMM tasks, the approach significantly improves functional correctness, version promotion stability, and downstream hardware performance, achieving state-of-the-art pass rates on GEMM preservation sets and superior synthesis scores.

Abstract

Large language models (LLMs) have improved Verilog generation from natural-language specifications, but most pipelines still treat generation as isolated sampling followed by functional checking. This is insufficient for practical RTL design, where useful Verilog must be correct, synthesizable, timing-conscious, and friendly to downstream hardware objectives. We present Verilog-Evolve, a feedback-driven framework for versioned Verilog refinement and cross-session skill evolution. For each task, Verilog-Evolve generates diverse minor candidates, evaluates them with executable feedback from functional simulation, Yosys synthesis, ABC timing proxy, and optional GEMM metrics, then promotes the best candidate into a major version under configurable scoring. To improve across tasks, the system maintains modular skill guidance, retrieves skills according to task and feedback context, and evolves candidate skills from logged histories through create/improve/skip decisions and verifier reports. Experiments on VerilogEval and mixed-precision GEMM tasks show that Verilog-Evolve improves final functional success and promotion stability while producing more downstream-friendly RTL under open-source synthesis, timing-proxy, and netlist-level GEMM objectives. Validation-gated skill evolution further improves GEMM downstream quality and achieves the best downstream score and GEMM held-out pass rate among the evaluated skill modes.

Problem

• Verilog generation
• RTL design
• functional correctness
• synthesizability
• timing-awareness

Innovation

• feedback-driven refinement
• skill evolution
• Verilog generation
• RTL optimization
• downstream-aware synthesis