Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification

2026-02-17

AI Summary

This work addresses the challenge that current large language models (LLMs) often produce low-quality SystemVerilog assertions with insufficient functional coverage due to a limited understanding of integrated circuit (IC) design semantics. To overcome this, the authors propose CoverAssert, a framework that constructs a lightweight joint embedding by integrating semantic features of assertions with structural features from their abstract syntax trees (ASTs). This embedding enables clustering and subsequent mapping back to functional specifications to evaluate coverage quality. A closed-loop feedback mechanism based on functional coverage is then established to guide the LLM in iteratively refining assertions for uncovered functionality. Experiments on four open-source designs demonstrate that integrating CoverAssert yields average improvements of 9.57%, 9.64%, and 15.69% in branch, statement, and toggle coverage, respectively.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Natural Language Processing: (Large) Language Models

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Search and Retrieval-Augmented AI: Search Tool Learning with LLM: Teaching LLMs to invoke search and make use of retrieved information

Abstract

While leveraging LLMs to automatically generate SystemVerilog assertions (SVAs) from natural language specifications holds great potential, existing techniques face a key challenge: LLMs often lack sufficient understanding of IC design, leading to poor assertion quality in a single pass. Therefore, verifying whether the generated assertions effectively cover the functional specifications and designing feedback mechanisms based on this coverage remain significant hurdles. To address these limitations, this paper introduces CoverAssert, a novel iterative framework for optimizing SVA generation with LLMs. The core contribution is a lightweight mechanism for matching generated assertions with specific functional descriptions in the specifications. CoverAssert achieves this by clustering the joint representations of semantic features of LLM-generated assertions and structural features extracted from abstract syntax trees (ASTs) about signals related to assertions, and then mapping them back to the specifications to analyze functional coverage quality. Leveraging this capability, CoverAssert constructs a feedback loop based on functional coverage to guide LLMs in prioritizing uncovered functional points, thereby iteratively improving assertion quality. Experimental evaluations on four open-source designs demonstrate that integrating CoverAssert with state-of-the-art generators, AssertLLM and Spec2Assertion, achieves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.

Problem

• LLM
• SystemVerilog assertion
• functional coverage
• verification
• natural language specification

Innovation

• LLM-based assertion generation
• functional coverage
• syntax-semantic representation
• iterative feedback
• SystemVerilog assertion