CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems

2026-06-24

AI Summary

This work addresses the challenges of uncontrolled worst-case processor latency and highly variable task execution times in mixed-criticality systems by introducing, for the first time, three real-time microarchitectural enhancements to the open-source CVA6 (RV64GC) processor. These include a TLB with partition locking support, a dynamically reconfigurable scratchpad mode for the L1 cache, and an enhanced interrupt controller featuring hardware-assisted context stacking. Together, these mechanisms ensure deterministic memory access and substantially reduce interrupt response latency. Experimental results demonstrate that with these real-time features enabled, interrupt latency is reduced to 12 cycles—tenfold lower than that of the baseline CVA6—achieving timing predictability comparable to Arm Cortex-M class processors.

Abstract

This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implements the rv64gch ISA and features advanced support for real-time execution, including TLB partitioning and locking for predictable address translation, a dynamically reconfigurable scratchpad mode in the L1 caches for deterministic memory access, and low-latency interrupt handling via an enhanced interrupt controller combined with hardware-assisted context stacking. With real-time features enabled, CVA6-RT achieves an interrupt latency of 12 cycles, comparable to that of simpler Arm Cortex-M microcontrollers, and 10x lower than the baseline CVA6 core.

Problem

• Mixed-Criticality Systems
• Worst-Case Latency
• Timing Predictability
• Real-Time Execution
• Interrupt Latency

Innovation

• real-time processor
• mixed-criticality systems
• TLB partitioning
• scratchpad memory
• low-latency interrupt