Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC

2024-07-08

IEEE Transactions on Nuclear Science

AI Summary

This study addresses the high-reliability requirements of automotive and aerospace applications by evaluating the single-event upset (SEU) tolerance of a 28 nm RISC-V SoC under atmospheric neutron and 200 MeV proton irradiation. Method: We propose a synergistic validation methodology combining radiation testing with gate-level fault injection, and for the first time integrate an ECC memory scrubber and a triple-core lockstep (TCLS) mechanism into a 28 nm RISC-V SoC to enable hardware-level closed-loop reliability verification. Contribution/Results: Experimental results show an SEU cross-section of only 1.09×10⁻¹⁴ cm²/bit for ECC-protected memory and a TCLS error-correction cross-section of 3.23×10⁻¹¹ cm²; the SoC achieves a functional correctness rate of 99.10%, while the TCLS core maintains 100% correctness. This work establishes a reproducible fault-tolerant design paradigm and a quantitative verification benchmark for trustworthy RISC-V deployment in harsh radiation environments.

Technology Category

• Machine Learning: Hardware-aware ML
• Intelligent Robots: Multimodal Perception & Sensor Fusion
• Computer Vision: Adversarial Attacks & Robustness

Application Category

• Security and Privacy: Large-scale security measurements
• Responsible Web: Measurement, analysis, and circumvention of Web censorship
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires characterization under controlled radiation doses to accurately quantify the fault tolerance of the fabricated designs. This work analyzes the Trikarenos design, a SoC implemented in TSMC 28nm, for single event upset (SEU) vulnerability under atmospheric neutron and 200 MeV proton radiation, comparing these results to simulation-based fault injection. All faults in error correction codes (ECC) protected memory are corrected by a scrubber, showing an estimated cross-section per bit of up to $1.09 imes 10^{-14}$ cm$^2$ bit$^{-1}$. Furthermore, the triple-core lockstep (TCLS) mechanism implemented in Trikarenos is validated and is shown to correct errors affecting a cross-section up to $3.23 imes 10^{-11}$ cm$^2$, with the remaining uncorrectable vulnerability below $5.36 imes 10^{-12}$ cm$^2$. When augmenting the experimental analysis of fabricated chips with gate-level fault injection in simulation, 99.10 % of injections into the SoC produced correct results, while 100 % of injections in the TCLS-protected cores were handled correctly. With 12.28 % of all injected faults leading to a TCLS recovery, this indicates an approximate effective flip-flop cross-section of up to $1.28 imes 10^{-14}$ cm$^2$/FF.

Problem

• Assessing fault tolerance of RISC-V SoC under radiation
• Validating error correction in memory and triple-core lockstep
• Comparing experimental radiation results with simulation-based fault injection

Innovation

• 28nm RISC-V SoC with fault-tolerant design
• Triple-core lockstep mechanism for error correction
• Radiation testing and simulation-based fault injection